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LP621024DX-70LLT 参数 Datasheet PDF下载

LP621024DX-70LLT图片预览
型号: LP621024DX-70LLT
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8位CMOS SRAM [128K X 8 BIT CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 16 页 / 186 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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LP621024D-T Series
AC Characteristics
(T
A
= -25°C to + 85°C, VCC = 5V
±
10%)
Symbol
Parameter
LP621024D-55LLT
Min.
Read Cycle
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
Write Cycle
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
55
50
0
50
40
0
0
25
0
5
-
-
-
-
-
-
25
-
-
-
70
60
0
60
50
0
0
30
0
5
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
Output Enable to Output in Low Z
Chip Disable to Output in High Z
CE1
CE2
Output Enable to Output Valid
Chip Enable to Output in Low Z
CE1
CE2
Read Cycle Time
Address Access Time
Chip Enable Access Time
CE1
CE2
55
-
-
-
-
10
10
5
0
0
0
5
-
55
55
55
30
-
-
-
20
20
20
-
70
-
-
-
-
10
10
5
0
0
0
5
-
70
70
70
35
-
-
-
25
25
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
LP621024D-70LLT
Min.
Max.
Unit
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
, and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(August, 2001, Version 1.0)
5
AMIC Technology, Inc.