LP621024D-I Series
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5 ns
1.5V
See Figures 1 and 2
+5V
1800Ω
I/O
I/O
+5V
1800Ω
990Ω
30pF*
990Ω
5pF*
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for t
CLZ1
,
t
CLZ2
, t
OHZ
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
WHZ
, and t
OW
Data Retention Characteristics
(T
A
= -40°C to 85°C)
Symbol
V
DR1
V
DR2
VCC for Data Retention
Parameter
Min.
2.0
2.0
Max.
5.5
5.5
Unit
V
V
Conditions
CE1
≥
VCC - 0.2V
CE2
≤
0.2V
CE1
≥
VCC - 0.2V or
CE1
≤
0.2V
VCC = 2.0V,
CE1
≥
VCC - 0.2V
CE2
≥
VCC - 0.2V
V
IN
≥
0V
VCC = 2.0V
CE2
≤
0.2V
V
IN
≥
0V
See Retention Waveform
I
CCDR1
Data Retention Current
I
CCDR2
LL-Version
-
20**
µA
LL-Version
-
20**
µA
ns
ms
t
CDR
t
R
Chip Disable to Data Retention Time
Operation Recovery Time
I
CCDR
: Max.
0
5
-
-
** LP621024D-55LLI/70LLI
2µA at T
A
= 0°C to + 40
°C
PRELIMINARY
(August, 2002, Version 0.0)
11
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
