LP62S1024B-I Series
Timing Waveforms (continued)
Read Cycle 4
(1)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
CE1
5
t
OH
t
ACE1
t
CLZ15
CE2
t
ACE2
t
CLZ25
D
OUT
t
CHZ2
5
t
CHZ15
t
OHZ5
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
WE is high for Read Cycle.
Device is continuously enabled CE1 = V
IL
and CE2 = V
IH
.
Address valid prior to or coincident with CE1 transition low.
OE = V
IL
.
Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
CE2 is high.
CE1 is low.
Address valid prior to or coincident with CE2 transition high.
Write Cycle 1
(6)
(Write Enable Controlled)
t
WC
Address
t
AW
t
CW5
CE1
(4)
t
WR3
CE2
t
AS1
WE
(4)
t
WP2
t
DW
D
IN
t
WHZ
t
DH
t
OW
D
OUT
(August, 2004, Version 1.2)
8
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
