LP62S1024B-I Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
t
WC
Address
t
AW
t
CW5
CE1
t
AS1
(4)
t
WR3
CE2
(4)
t
CW5
t
WP2
WE
t
DW
D
IN
t
DH
t
WHZ7
D
OUT
Notes: 1.
2.
3.
4.
t
AS
is measured from the address valid to the beginning of Write.
A Write occurs during the overlap (t
WP
) of a low CE1, a high CE2 and a low WE .
t
WR
is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. t
CW
is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = V
IL
)
7. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
(August, 2004, Version 1.2)
9
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
