LP62S1024A-T Series
Block Diagram
A0
VCC
GND
A14
A15
A16
ROW
DECODER
512 X 2048
MEMORY ARRAY
I/O
1
INPUT DATA
CIRCUIT
COLUMN I/O
I/O
8
CE2
CE1
OE
WE
CONTROL
CIRCUIT
Pin Descriptions - SOP
Pin No.
1
2 - 12, 23,
25 - 28, 31
13 - 15,
17 - 21
16
22
24
29
30
32
Symbol
NC
A0 - A16
Description
No Connection
Address Inputs
Pin Description – TSOP/TSSOP
Pin No.
1 - 4, 7,
10 - 20, 31
5
6
8
9
21 - 23,
25 - 29
24
30
32
Symbol
A0 - A16
WE
CE2
VCC
NC
I/O
1
- I/O
8
GND
CE1
OE
Description
Address Inputs
Write Enable
Chip Enable
Power Supply
No Connection
Data Input/Outputs
Ground
Chip Enable
Output Enable
I/O
1
- I/O
8
GND
CE1
OE
WE
CE2
VCC
Data Input/Outputs
Ground
Chip Enable
Output Enable
Write Enable
Chip Enable
Power Supply
(August, 2001, Version 1.0)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
