LP62S16128B-T Series
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
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Operating voltage: 2.7V to 3.6V
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Access times: 55/70 ns (max.)
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Current:
Very low power version: Operating: 55ns 40mA (max.)
70ns 35mA (max.)
Standby:
10µA (max.)
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Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 2V (min.)
Available in 44-pin TSOP and 48-ball CSP (6 x 8 mm)
packages
General Description
The LP62S16128B-T is a low operating current
2,097,152-bit static random access memory organized as
131,072 words by 16 bits and operates on low power
voltage from 2.7V to 3.6V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
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TSOP
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CSP (Chip Size Package)
48-pin Top View
A4
A3
A2
A1
A0
CE
I/O
1
I/O
2
I/O
3
I/O
4
VCC
GND
I/O
5
I/O
6
I/O
7
I/O
8
WE
A16
A15
A14
A13
A12
1
2
3
4
44
43
42
41
A5
A6
A7
OE
HB
LB
I/O
16
I/O
15
I/O
14
I/O
13
GND
VCC
I/O
12
I/O
11
I/O
10
I/O
9
NC
A8
A9
A10
A11
NC
1
A
B
C
D
E
F
G
H
LB
I/O
9
I/O
10
GND
VCC
I/O
15
I/O
16
NC
2
OE
HB
I/O
11
I/O
12
I/O
13
I/O
14
NC
A8
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
I/O
2
I/O
4
I/O
5
I/O
6
WE
A11
6
NC
I/O
1
I/O
3
VCC
GND
I/O
7
I/O
8
NC
LP62S16128BV-T
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
(August, 2001, Version 1.0)
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AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
