LP62S1664C Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
t
WC
Address
t
AW
t
CW
CE
t
WR
3
t
AS
1
t
BW
2
HB, LB
t
WP
WE
t
DW
t
DH
DATA IN
t
WHZ
4
t
OW
DATA OUT
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
, t
BW
) of a low CE , WE and ( HB and, or LB ).
3. t
WR
is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured
±500mV
from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(February, 2002, Version 0.0)
10
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
