LP62S2048-T Series
Block Diagram
A0
VCC
GND
A15
A16
A17
ROW
DECODER
1024 X 2048
MEMORY ARRAY
I/O
1
INPUT DATA
CIRCUIT
COLUMN I/O
I/O
8
CE2
CE1
OE
WE
CONTROL
CIRCUIT
Pin Description - SOP
Pin No.
1 - 12, 23,
25 - 28, 31
13 - 15,
17 - 21
16
22
24
29
30
32
Symbol
Description
Pin Descriptions - TSOP/TSSOP
Pin No.
1 - 4, 7,
9 - 20, 31
5
Symbol
A0 - A17
WE
CE2
VCC
NC
I/O
1
- I/O
8
GND
CE1
OE
Description
Address Inputs
Write Enable
Chip Enable
Power Supply
No Connection
Data Input/Outputs
Ground
Chip Enable
Output Enable
A0 - A17
Address Inputs
I/O
1
- I/O
8
GND
CE1
OE
WE
CE2
VCC
Data Input/Outputs
6
Ground
8
Chip Enable
Output Enable
Write Enable
Chip Enable
Power Supply
9
21 - 23,
25 - 29
24
30
32
(August, 2001, Version 1.0)
2
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
