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LP62S2048X-10LT 参数 Datasheet PDF下载

LP62S2048X-10LT图片预览
型号: LP62S2048X-10LT
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×8位的低电压CMOS SRAM [256K X 8 BIT LOW VOLTAGE CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 192 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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LP62S2048-T Series
AC Characteristics
Symbol
(T
A
= -25°C to + 85°C, VCC = 2.7V to 3.3V)
Parameter
LP62S2048-70LT/LLT
Min.
Read Cycle
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
Write Cycle
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
70
60
0
60
50
0
0
30
0
5
-
-
-
-
-
-
25
-
-
-
100
80
0
80
60
0
0
40
0
5
-
-
-
-
-
-
35
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
Output Enable to Output in Low Z
Chip Disable to Output in High Z
CE1
CE2
Output Enable to Output Valid
Chip Enable to Output in Low Z
CE1
CE2
Read Cycle Time
Address Access Time
Chip Enable Access Time
CE1
CE2
70
-
-
-
-
10
10
5
0
0
0
10
-
70
70
70
35
-
-
-
25
25
25
-
100
-
-
-
-
10
10
5
0
0
0
10
-
100
100
100
50
-
-
-
35
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max.
LP62S2048-10LT/LLT
Min.
Max.
Unit
Notes: t
CHZ1
, t
CHZ2
, t
OHZ
, and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(August, 2001, Version 1.0)
6
AMIC Technology, Inc.