AMS73CAG01808RA
Mode Register MR0
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It con-
trols burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various appli-
cations. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0, BA1 and BA2, while
controlling the states of address pins according to the table below.
BA
2
BA
1
BA
0
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Field
0*
1
0
0
0*
1
PPD
WR
DLL
TM
CAS Latency
RBT
CL
BL
Mode Register 0
A8
0
1
DLL Reset
No
Yes
A7
0
1
mode
Normal
Test
A3
0
1
Read Burst Type
Nibble Sequential
Interleave
A1
0
0
1
1
A0
0
1
0
1
BL
8 (Fixed)
4 or 8(on the fly)
4 (Fixed)
Reserved
A12
0
1
DLL Control for
Precharge PD
Slow exit (DLL off)
Fast exit (DLL on)
Write recovery for autoprecharge
A11
0
0
0
A10
0
0
1
1
0
0
1
1
A9
0
1
0
1
0
1
0
1
WR(cycles)
Reserved
5
*2
6
*2
7
*2
8
*2
10
*2
12
*2
Reserved
CAS Latency
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
A2
0
0
0
0
0
0
0
0
Latency
Reserved
5
6
7
8
9
10
11(Optional for
DDR3-1600)
BA1
0
0
1
1
BA0
0
1
0
1
MRS mode
MR0
MR1
MR2
MR3
0
1
1
1
1
*1 : BA2 and A13 are reserved for future use and must be programmed to 0 during MRS.
*2 : WR(write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the
next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in the mode register must be programmed to be equal or
larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
AMS73CAG01808RA
Rev. 1.0 December 2010
7
AMS [ Advanced Monolithic Systems Ltd ]
