AMS73CAG01808RA
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and
CAS write latency (CWL). The Mode Register 2 is written by asserting low on CS, RAS, CAS, WE, high on
BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
BA2
BA1
BA
0
A
13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*
1
1
0
0*
1
Rtt_WR
0*
1
SRT ASR
CWL
PASR*
2
Mode Register 2
A2 A1 A0
A7
0
1
Self-refresh temperature range (SRT)
Normal operating temperature range
Extend temperature self-refresh (Optional)
0
0
0
0
A6
0
1
Auto Self-refresh (ASR)
Manual SR Reference (SRT)
ASR enable (Optional)
1
1
1
1
A10 A9
0
0
1
1
0
1
0
1
Rtt_WR
*2
Dynamic ODT off
(Write does not affect Rtt value)
RZQ/4
RZQ/2
Reserved
A5 A4 A3
0
0
0
0
BA1
0
0
1
1
BA0
0
1
0
1
MRS mode
MR0
MR1
MR2
MR3
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
Partial Array Self Refresh (Optional)
0 Full Array
1 HalfArray (BA[2:0]=000,001,010, &011)
0 Quarter Array (BA[2:0]=000, & 001)
1 1/8th Array (BA[2:0] = 000)
0 3/4 Array (BA[2:0] = 010,011,100,101,110, & 111)
1 HalfArray (BA[2:0] = 100, 101, 110, &111)
0 Quarter Array (BA[2:0]=110, &111)
1 1/8th Array (BA[2:0]=111)
CAS write Latency (CWL)
5 (tCK(avg)
≥
2.5ns)
6 (2.5ns
>tCK(avg) ≥
1.875ns)
7 (1.875ns>tCK(avg)
≥
1.5ns)
8 (1.5ns>tCK(avg)
≥
1.25ns)
Reserved
Reserved
Reserved
Reserved
* 1 : BA2, A8, A11 ~ A13 are RFU and must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
AMS73CAG01808RA
Rev. 1.0 December 2010
9
AMS [ Advanced Monolithic Systems Ltd ]
