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AMS73CAG01168RALJI9E 参数 Datasheet PDF下载

AMS73CAG01168RALJI9E图片预览
型号: AMS73CAG01168RALJI9E
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能的1Gbit DDR3 SDRAM [HIGH PERFORMANCE 1Gbit DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 31 页 / 683 K
品牌: AMS [ Advanced Monolithic Systems Ltd ]
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AMS73CAG01808RA
AMS73CAG01808RA
HIGH PERFORMANCE 1Gbit DDR3 SDRAM
8 BANKS X 16Mbit X 8
- H7
DDR3-1066
Clock Cycle Time ( t
CK6, CWL=5
)
Clock Cycle Time ( t
CK7, CWL=6
)
Clock Cycle Time ( t
CK8, CWL=6
)
Clock Cycle Time ( t
CK9, CWL=7
)
Clock Cycle Time ( t
CK10, CWL=7
)
System Frequency (f
CK max
)
2.5 ns
1.875 ns
1.875 ns
-
-
533 MHz
- I9
DDR3-1333
2.5 ns
1.875 ns
1.875 ns
1.5 ns
1.5 ns
667 MHz
Specifications
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Features
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Density : 1G bits
Organization : 16M words x 8 bits x 8 banks
Package :
- 78-ball FBGA
- Lead-free (RoHS compliant) and Halogen-free
Power supply : VDD, VDDQ = 1.5V ± 0.075V
Data rate : 1333Mbps/1066Mbps (max.)
1KB page size
- Row address: A0 to A13
- Column address: A0 to A9
Eight internal banks for concurrent operation
Interface : SSTL_15
Burst lengths (BL) : 8 and 4 with Burst Chop (BC)
Burst type (BT) :
- Sequential (8, 4 with BC)
- Interleave (8, 4 with BC)
CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11
CAS Write Latency (CWL) : 5, 6, 7, 8
Precharge : auto precharge option for each burst ac-
cess
Driver strength : RZQ/7, RZQ/6 (RZQ = 240
Ω)
Refresh : auto-refresh, self-refresh
Refresh cycles :
- Average refresh period
7.8
μs
at 0°C
Tc
+85°C
3.9
μs
at +85°C < Tc
+95°C
Operating case temperature range
- Tc = 0°C to +95°C
-
-
-
-
-
-
-
-
-
-
-
-
-
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted CAS by programmable additive latency for bet-
ter command and data bus efficiency
On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
RESET pin for Power-up sequence and reset function
SRT range : Normal/extended
Programmable Output driver impedance control
Device Usage Chart
Operating
Temperature
Range
0°C
Tc
95°C
-40°C
Tc
95°C
AMS73CAG01808RA
Rev.1.0 December 2010
Package Outline
78-ball FBGA
- H7
Speed
- I9
1
Std.
Power
L
Temperature
Mark
Blank
I