AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode,
applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, enabling or disabling the
SPI-compatible interface, setting the blinking rate, and resetting the blink timing.
Note:
At power-up the Feature Register is initialized to 0.
Table 19. Feature Register Summary
D7
D6
D5
D4
D3
D2
D1
D0
blink_
start
sync
blink_
freq_sel
blink_en
NU
decode_sel
reg_res
clk_en
Table 20. Feature Register Bit Descriptions (Address (HEX) = 0xXE)
Addr: 0xXE
Bit
Feature Register
Enables and disables various device features.
Bit Name
Default
Access
Bit Description
External clock active.
clk_en
0
R/W
0 = Internal oscillator is used for system clock.
1 = Pin CLK of the serial interface operates as system clock input.
Resets all control registers except the Feature Register.
0 = Reset Disabled. Normal operation.
reg_res
0
R/W
1 = All control registers are reset to default state (except the Feature
Register) identically after power-up.
Note:
The Digit Registers maintain their data.
Selects display decoding for the selected digits (Table
decode_sel
0 = Enable Code-B decoding (see
0
R/W
1 = Enable HEX decoding (see
NU
Not used
Enables blinking.
blink_en
0
R/W
0 = Disable blinking. 1 = Enable blinking.
Sets blink with low frequency (with the internal oscillator enabled):
blink_freq_sel
0 = Blink period typically is 1 second (0.5s on, 0.5s off).
0
R/W
1 = Blink period is 2 seconds (1s on, 1s off).
Synchronizes blinking on the rising edge of pin LD. The multiplex and
blink timing counter is cleared on the rising edge of pin LD. By setting
sync
0
R/W
this bit in multiple devices, the blink timing can be synchronized across
all the devices.
Start Blinking with display enabled phase. When bit D4 (blink_en) is set,
bit D7 determines how blinking starts.
blink_start
0
R/W
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
D0
D1
D2
D3
D4
D5
D6
D7
No-Op Register (0xX0)
The No-Op Register is used when multiple AS1116 devices are cascaded in order to support displays with more than 8
digits. The cascading must be done in such a way that all SDO pins are connected to SDI of the next AS1116 (see
The LD and SCL signals are connected to all devices.
For example, if five devices are cascaded, in order to perform a write operation to the fifth device, the write-command
must be followed by four no-operation commands. When the LD signal goes high, all shift registers are latched. The
first four devices will receive no-operation commands and only the fifth device will receive the intended operation com-
mand, and subsequently update its register.
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