D a ta s h e e t
A S 11 6 0 / A S 11 6 1
2 0 M H z - 6 6 M H z , 1 0 - B i t B u s , I E E E 11 4 9 . 1 ( J TA G )
C o m p l i a n t LV D S S e r i a l i z e r / D e s e r i a l i z e r
1 General Description
The AS1160 (serializer) is designed to convert 10-bit
wide parallel LVCMOS/LVTTL data bus signals into a
single high-speed LVDS serial data stream with clock.
The AS1161 (deserializer) transforms the high-speed
LVDS serial data stream back into a 10-bit wide parallel
data bus with recovered parallel clock.
Both devices are compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture
(including the defined boundary-scan test logic and test
access port consisting of Test Data Input, Test Data Out,
and Test Mode Select, Test Clock, and Test Reset).
The devices also feature an at-speed BIST mode which
allows the interconnects between the serializer and
deserializer to be verified at-speed.
The single differential-pair data-path makes PCB design
easier, and reduced cable/PCB-trace count and connec-
tor size significantly reduce cost. Since one output trans-
mits clock and data bits serially, clock-to-data and data-
to-data skew are eliminated.
Powerdown mode reduces supply current when both
devices are idle.
Both devices are available in a CTBGA 49-bumps pin
package.
2 Key Features
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Serial Bus LVDS Data Rate: 660 Mbps @ 66MHz
Clock
10-bit Parallel Interface
Synchronization Mode and Lock Indicator
Programmable Edge Trigger on Clock
High Impedance on Rx Inputs during Poweroff
Bus LVDS Serial Output Load: 28Ω
IEEE 1149.1 (JTAG) Compliant and At-Speed BIST
Test Mode
Clock Recovery from PLL Lock to Random Data
Patterns
Guaranteed Transition each Data Transfer Cycle
Chipset (Tx + Rx) Power Consumption: < 500 mW
@ 66MHz
Single Differential-Pair eliminates Multi-Channel
Skew
Flow-Through Pinout for Simple PCB Layout
Small CTBGA 49-bumps Package
3 Applications
The devices are ideal for cellular phone base stations,
add drop muxes, digital cross-connects. DSLAMs, net-
workswitches and routers or backplane interconnect.
Figure 1. Block Diagrams
10
DIN0:9
TCKR/FN
TCLK
PLL
Timing &
Control
Input
Latch
Parallel-
to-Serial
DO+
DO-
LVDS
RI+
RI-
REFCLK
REN
LOCKN
SYNC1
SYNC2
TDI
TDO
TMS
TCK
IEEE 1149.1
Test Access
Port
TRSTN
TRSTN
IEEE 1149.1
Test Access
Port
Clock
Recovery
RCLK
RCKR/FN
TDI
TDO
TMS
TCK
Parallel-
to-Serial
Output
Latch
10
ROUT0:9
PLL
DEN
Timing &
Control
AS1160
AS1161
Revision 1.01
1 - 29
AMSCO [ AUSTRIAMICROSYSTEMS AG ]
