AS1329
Data Sheet
- Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
SW 1
6 V
IN
GND 2
AS1329
5 V
OUT
FB 3
4 SHDNN
Pin Descriptions
Table 2. Pin Descriptions
Pin
Name
Pin
Number
Description
Switch Pin.
Connect an inductor between this pin and V
IN
. Keep the PCB
trace lengths as short and wide as is practical to reduce EMI and voltage
overshoot. If the inductor current falls to zero, or pin SHDNN is low, an
internal 100Ω anti-ringing switch is connected from this pin to V
IN
to
minimize EMI.
Note:
An optional Schottky diode can be connected between this pin and
V
OUT
.
Signal and Power Ground.
Provide a short, direct PCB path between this
pin and the negative side of the output capacitor(s).
Feedback Pin.
Feedback input to the g
m
error amplifier. Connect a resistor
divider tap to this pin. The output voltage can be adjusted from 2.5 to 5V by:
V
OUT
= 1.23V[1 + (R
1
/R
2
)]
Shutdown Pin.
Logic controlled shutdown input.
1 = Normal operation, 1.2MHz typical operating frequency.
0 = Shutdown; quiescent current <1µA. If SHDNN is undefined, pin SW may
ring.
Note:
In a typical application, SHDNN should be connected to V
IN
through a
1MΩ pull-up resistor.
Output Voltage Sense Input and Drain of the Internal PMOS
Synchronous Rectifier.
Bias is derived from V
OUT
when V
OUT
exceeds V
IN
.
PCB trace length from V
OUT
to the output filter capacitor(s) should be as
short and wide as is practical.
Input Voltage.
The AS1329 gets its start-up bias from V
IN
unless V
OUT
exceeds V
IN
, in which case the bias is derived from V
OUT
. Thus, once
started, operation is completely independent from V
IN
. Operation is only
limited by the output power level and the internal series resistance of the
supply.
SW
1
GND
FB
2
3
SHDNN
4
V
OUT
5
V
IN
6
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