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AS1713 参数 Datasheet PDF下载

AS1713图片预览
型号: AS1713
PDF下载: 下载PDF文件 查看货源
内容描述: 差分放大器的10MHz , 10V / μs的轨至轨I / O [Difference Amplifier, 10MHz, 10V/μs, Rail-to-Rail I/O]
分类和应用: 放大器
文件页数/大小: 15 页 / 1738 K
品牌: AMSCO [ AUSTRIAMICROSYSTEMS AG ]
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AS1713
D i f f e r e n c e A m p l i f i e r, 1 0 M H z , 1 0 V / µ s , R a i l - t o - R a i l I / O
w i t h S h u td o w n
D a ta S he e t
1 General Description
The AS1713 is a low cost cmos difference amplifier pro-
viding extended common mode voltage range for a sin-
gle rail 5V supply. Resistor trimming during final test
ensures a typical common mode rejection of 60dB. Low
input bias currents, 10MHz gain bandwidth, low total
harmonic distortion (THD) and a rail-to-rail output drive
capability of typically 200mA (@ 5V supply) provide sup-
port for a number of signal processing applications such
as audio line receivers, ground loop breakers and cur-
rent sensing. Linearity is suitable for 12bit ADC mea-
surement.
A classical single amplifier approach ensures that the
differential gain is determined by a simple ratio of two
internal resistors. A fixed gain of x1 is available.
Single ended input resistance is equalised (10kΩ ±10%)
at each input terminal. This feature provides additional
common mode rejection when long balanced input
cables connect at the input.
A EN pin reduces the quiescent current of the device.
2 Key Features
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Constant Output Drive Capability: 50mA
Rail-to-Rail Input and Output
Supply Current: 1.6mA
Single-Supply Operation: 2.7 to 5.5V
Voltage Gain: 1
Gain-Bandwidth Product: 10MHz
High Slew Rate: 10V/µs
Power-Supply Rejection Ratio: -70dB
Common Mode Rejection Ratio: -60dB
No Phase Reversal for Overdriven Inputs
Unity-Gain Stable for Capacitive Loads: Up to 100pF
Shutdown Mode Current: 1nA
MLPD (2x2mm) 8-pin package
3 Applications
The device is ideal for headphone amplifiers with ground
interference rejection, infotainment high drive audio line
buffers with ground interference rejection, audio differ-
ential-to-single-ended conversion and instrumentation
amplifier back-end.
Figure 1. Block Diagram
VDD
INN
R
1
R
2
SENSE
EN
AS1713
+
OUT
INP
R
3
R
4
REF
VSS
www.austriamicrosystems.com
Revision 1.01
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