AS8202NF TTP-C2NF
Data Sheet
- D e t a i l e d D e s c r i p t i o n
Table 5. Host Interface Ports
Pin Name
OEB
READYB
INTB
RAM_CLK_TESTSE
USE_RAM_CLK
Mode
In
out (open drain)
out (open drain)
in
in
Width
1
1
1
1
1
Comment
CNI output enable, active low
CNI ready, active low
CNI interrupt, time signal, active low
HOST clock
HOST clock pin enable
Asynchronous READYB
permits the shortest possible bus cycle but eventually requires signal synchronization in the
application. Connect USE_RAM_CLK to V
SS
to enable this mode of operation.
Synchronous READYB
uses an external clock (usually the host processor’s bus clock) for synchronization of the
signal, eliminating external synchronization logic. Connect USE_RAM_CLK to V
DD
and RAM_CLK_TESTSE to the
host processor's bus clock to enable this mode of operation.
Note:
Due to possible metastability occurrence, it is not recommended to be used in safety critical systems.
Table 6. Asynchronous DPRAM interface
Symbol
Tc
1a
2a
1b
2b
3
4
5
6
7a
7b
8
9
10
11a
11b
11c
12
13
Parameter
Controller Cycle Time
Input Valid to CEB, WEB
(Setup Time)
CEB, WEB to Input Invalid
(Hold Time)
Input Rising to CEB, WEB
Falling
CEB, WEB Rising to Input
Falling
Write Access Time (CEB,
WEB to READYB)
CEB, WEB de-asserted to
READYB de-asserted
Input Valid to CEB, OEB
(Setup Time)
CEB, OEB to Input Invalid
(Hold Time)
Input Rising to CEB, OEB
Falling
CEB, OEB Rising to Input
Falling
Read Access Time (CEB,
OEB to READYB)
CEB, OEB asserted to
signal asserted
CEB, OEB de-asserted to
signal de-asserted
READYB, D skew
RAM_CLK_TESTSE
Rising to READYB Falling
USE_RAM_CLK=1
3.7
A[11:0]
A[11:0]
CEB, WEB, OEB
CEB, WEB, OEB
min = 1.5 Tc, max = 8 Tc
D[15:0]
D[15:0]
READYB
5
2
5
Conditions
Min
Typ
25
Max
Units
ns
ns
A[11:0]
D[15:0]
A[11:0]
D[15:0]
CEB, WEB, OEB
CEB, WEB, OEB
min = 1 Tc, max = 4 Tc
5
3
4
5
5
1
ns
ns
ns
100
9.4
ns
ns
ns
ns
ns
ns
200
8.4
8
8.8
±2
13.5
ns
ns
ns
ns
ns
,2
25
5
37.5
4.0
3.8
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