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PA7572 参数 Datasheet PDF下载

PA7572图片预览
型号: PA7572
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程电可擦除逻辑阵列 [Programmable Electrically Erasable Logic Array]
分类和应用:
文件页数/大小: 10 页 / 323 K
品牌: ANACHIP [ ANACHIP CORP ]
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Table 5. A.C. Electrical Characteristics Sequential
Symbol
t
SCI
t
SCX
t
COI
t
COX
t
HX
t
SK
t
AK
t
HK
t
SI
t
HI
t
PK
t
SPI
t
HPI
t
SD
t
HD
t
SDP
t
HDP
t
CK
t
CW
f
MAX1
f
MAX2
f
MAX3
f
MAX4
f
TGL
t
PR
t
ST
t
AW
t
RT
t
RTV
t
RTC
t
RW
t
RESET
Parameter
6,1
Internal set-up to system clock - LCC
(t
AL
+ t
SK
+ t
LC
- t
CK
)
16
8
14
-20/I-20
Min
8
10
7
12
0
1
1
4
0
5
9
0
10
10
0
7
0
6
7
66.6
58.8
50.0
45.4
71.4
1
15
8
8
1
9
10
2
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
µs
Input (EXT.) set-up to system clock, - LCC (t
IA
+ t
SCI
)
System-clock to Array Int. - LCC/IOC/INC (t
CK
+t
LC
)
System-clock to Output Ext. - LCC (t
COI
+ t
LO
)
Input hold time from system clock - LCC
LCC Input set-up to async. clock - LCC
Clock at LCC or IOC - LCC output
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC (t
SK
- t
CK
)
Input hold time from system clock - IOC/INC (t
SK
- t
CK
)
Array input to IOC PCLK clock
Input set-up to PCLK clock - IOC/INC (t
SK
-t
PK
-t
IA
)
Input hold from PCLK clock - IOC/INC (t
PK
+t
IA
-t
SK
)
Input set-up to system clock - IOC/INC Sum-D
(
t
IA
+ t
AL
+ t
LC
+ t
SK
- t
CK
)
Input hold time from system clock - IOC Sum-D
Input set-up to PCLK clock - IOC Sum-D
(t
IA
+ t
AL
+ t
LC
+ t
SK
- t
PK
)
Input hold time from PCLK clock - IOC Sum-D
System-clock delay to LCC/IOC/INC
System-clock low or high pulse width
Max. system-clock frequency Int/Int 1/(t
SCI
+ t
COI
)
Max. system-clock frequency Ext/Int 1/(t
SCX
+ t
COI
)
Max. system-clock frequency Int/Ext 1/(t
SCI
+ t
COX
)
Max. system-clock frequency Ext/Ext 1/(t
SCX
+ t
COX
)
Max. system-clock toggle frequency 1/(t
CW
+ t
CW
)
LCC presents/reset to LCC output
Input to Global Cell present/reset (t
IA
+ t
AL
+ t
PR
)
Asynch. preset/reset pulse width
Input to LCC Reg-Type (RT)
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (t
RT
+ t
RTV
)
Asynch. Reg-Type pulse width
Power-on reset time for registers in clear state
9
15
17
17
14
13
14
5
Anachip Corp.
www.anachip.com.tw
8/10
Rev. 1.0 Dec 16, 2004