欢迎访问ic37.com |
会员登录 免费注册
发布采购

PEEL22CV10API-15 参数 Datasheet PDF下载

PEEL22CV10API-15图片预览
型号: PEEL22CV10API-15
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS可编程电可擦除逻辑器件 [CMOS Programmable Electrically Erasable Logic Device]
分类和应用: 可编程逻辑器件光电二极管时钟
文件页数/大小: 10 页 / 338 K
品牌: ANACHIP [ ANACHIP CORP ]
 浏览型号PEEL22CV10API-15的Datasheet PDF文件第2页浏览型号PEEL22CV10API-15的Datasheet PDF文件第3页浏览型号PEEL22CV10API-15的Datasheet PDF文件第4页浏览型号PEEL22CV10API-15的Datasheet PDF文件第5页浏览型号PEEL22CV10API-15的Datasheet PDF文件第6页浏览型号PEEL22CV10API-15的Datasheet PDF文件第7页浏览型号PEEL22CV10API-15的Datasheet PDF文件第9页浏览型号PEEL22CV10API-15的Datasheet PDF文件第10页  
Table 9. A.C. Electrical Characteristics
Over the Operating Range
8,11
-1/I-7
-10/I-10
-15/I-15
Symbol
Parameter
Min Max Min Max Min Max
t
PD
t
OE
t
OD
t
CO1
t
CO2
t
CF
t
SC
t
HC
t
CL
, t
CH
t
CP
f
MAX1
f
MAX2
f
MAX3
t
AW
t
AP
t
AR
t
RESET
Input to non-registered output
Input to output enable
5
5
6
6
5
-25/I-25
Min Max
25
25
25
15
35
9
15
0
13
30
41.6
33.3
38.4
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
7.5
7.5
7.5
5.5
10
3.5
3
0
8
10
10
10
6
12
4
5
0
4
11
111
909
125
10
8
0
6
18
76.9
62.5
83.3
15
10
10
5
15
15
15
8
17
5
Input to output disable
Clock to Output
Clock to comb. output delay via
internal registered feedback
Clock to Feedback
Input or Feedback Setup to Clock
Input Hold After Clock
Clock Low Time, Click High Time
Min Clock Period Ext(t
SC
+t
CO1
)
Internal Feedback (1t
SC
+t
CF
)
External Feedback (1/t
CP
)
No Feedback (1/t
CL
+t
CH
)
5
12
12
12
5
5
3
8.5
142
117
166
7.5
7.5
7.5
5
Asynchronous Reset Pulse Width
Input to Asynchronous Reset
Asynch. Reset recovery time
Power-on Reset Time for registers
in Clear State
15
15
5
25
25
5
ns
ns
ns
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes
1. Minimum DC input is -0.5V, however inputs may undershoot to -2.0V for
periods less than 20ns.
2. V
I
and V
O
are not specified for program/verify operation.
3. Test points for Clock and V
CC
in t
R
, t
F
are referenced at 10% and 90%
levels.
4. I/O pins are 0V and 3V.
5. “Input” refers to an Input pin signal.
6. t
OE
is measured from input transition to V
REF
± 0.1V, t
OD
is measured from
input transition to V
OH
-0.1V or V
OL
+0.1V; V
REF
=V
L
see test loads in
Section 5 of the Data Book.
7. Capacitances are tested on a sample basis.
8. Test conditions assume: signal transition times of 3ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
9. Test one output at a time for a duration of less than 1sec.
10. ICC for a typical application: This parameter is tested with the device
programmed as an 8-bit Counter.
11. PEEL™ Device test loads are specified in Section 6 of this Data Book.
12. Parameters are not 100% tested. Specifications are based on initial
characterization and are tested after any design or process modifica-
tion which may affect operational frequency.
13. Available only for 22CV10A -15/I-15/-25/I-25 grades.
Anachip Corp.
www.anachip.com.tw
8/10
Rev. 1.0 Dec 16, 2004