ACD2204
LOGIC PROGRAMMING
Synthesizer Register Programming
The ACD2204 includes two PLL synthesizers. Each
synthesizer contains programmable Reference and
Main dividers, which allow a wide range of local
oscillator frequencies. The 22-bit registers that control
the dividers are programmed via a shared three-wire
bus, consisting of Data, Clock and Enable lines.
The data word for each register is entered serially
in order with the most significant bit (MSB) first and
the least significant bit (LSB) last. The rising edge
of the Clock pulse shifts each data value into the
register. The Enable line must be low for the duration
of the data entry, then set high to latch the data into
the register. (See Figure 4.)
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 7 indicates the register select bit settings used
to program each of the available registers.
Table 7: Register Select Bits
SELECT
BITS
S
2
0
0
1
1
S
1
0
1
0
1
DESTINATION REGISTER FOR
SERIAL DATA
Reference Divider Register for PLL2
Main Divider Register for PLL2
Reference Divider Register for PLL1
Main Divider Register for PLL1
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 8. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 9.
MSB
Table 8: Reference Divider Registers
21 20
19
18
17
16
15
14
13
12
11 10
9
8
7
6
5
4
3
2
LSB
22
1
Program Mode
D
5
D
4
D
3
D
2
D
1
R
15
R
14
R
13
Reference Divider Divide Ratio, R
R
12
R R
11 10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
Select
S
2
S
1
Table 9: Reference Divider R Counter Bits
DIVIDE
RATIO R
3
4
-
32767
R
15
0
0
-
1
R
14
0
0
-
1
R
13
0
0
-
1
R
12
0
0
-
1
R
11
0
0
-
1
R
10
0
0
-
1
R
9
0
0
-
1
R
8
0
0
-
1
R
7
0
0
-
1
R
6
0
0
-
1
R
5
0
0
-
1
R
4
0
0
-
1
R
3
0
1
-
1
R
2
1
0
-
1
R
1
1
0
-
1
Notes:
Divide ratios less than 3 are prohibited.
8
PRELIMINARY DATA SHEET - Rev 1.0
04/2003
ANADIGICS [ ANADIGICS, INC ]
