ACD2204
For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison
frequency are used to yield R
PLL1
= 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter
are R
PLL1
= 000000000010000.
Calculation of Main Divider Values
The values for the A and B counters are determined by the desired VCO output frequency for the local
oscillator and the phase detector comparison frequency:
N = f
VCO
/ f
PD
B = trunc(N / P)
A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.
The main divider ratio for the down converter, then, is N
PLL2
= 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the
ACD2204, B
PLL2
= trunc(16672 / 64) = 260, and A
PLL2
= 16672 - (260 x 64) = 32. These results give bit values
of B
PLL2
= 00100000100 and A
PLL2
= 0100000 for the B and A counters.
The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.
Therefore, N
PLL1
= 1587 MHz / 250 KHz = 6348, B
PLL1
= trunc(6348 / 64) = 99, and A
PLL1
= 6348 - (99 x 64) = 12.
These results give bit values of B
PLL1
= 00001100011 and A
PLL1
= 0001100 for the B and A counters.
Phase Detector Polarity
Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be
negative, and D1
PLL1
= 1. If the VCO for the down converter has a positive slope, the phase detector polarity for
PLL2 should be positive, and D1
PLL2
= 0.
In summary, for this example, the four register programming words are shown in Tables 16 and 17:
Table 16: PLL1 and PLL2 Reference Divider Register Bits
for Synthesizer Programming Example
MSB
LSB
22
21
20
19
18
17
16
15
14
13
12
11 10
9
8
7
6
5
4
3
2
1
Program
Mode
C
2
0
0
C
1
0
0
B B
11 10
0
0
0
0
B
9
1
0
Main Divider B Counter
B
8
0
0
B
7
0
1
B
6
0
1
B
5
0
0
B
4
0
0
B
3
1
0
B
2
0
1
B
1
0
1
A
7
0
0
Main Divider A Counter
A
6
1
0
A
5
0
0
A
4
0
1
A
3
0
1
A
2
0
0
A
1
0
0
Select
S
2
0
1
S
1
1
1
MSB
Table 17: PLL1 and PLL2 Main Divider Register Bits
for Synthesizer Programming Example
21 20
19
18
17
16
15
14
13
12
11 10
9
8
7
6
5
4
3
2
LSB
22
1
Program Mode
D
5
0
0
D
4
0
0
D
3
0
0
D
2
0
0
D
1
1
0
R
15
0
0
R
14
0
0
R
13
0
0
R
12
0
0
Reference Divider R Counter
R R
11 10
0
0
0
0
R
9
0
0
R
8
0
0
R
7
1
0
R
6
0
0
R
5
0
1
R
4
0
0
R
3
0
0
R
2
0
0
R
1
0
0
Select
S
2
0
1
S
1
0
0
11
PRELIMINARY DATA SHEET - Rev 1.0
04/2003
ANADIGICS [ ANADIGICS, INC ]
