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AS29LV800B-90TI 参数 Datasheet PDF下载

AS29LV800B-90TI图片预览
型号: AS29LV800B-90TI
PDF下载: 下载PDF文件 查看货源
内容描述: 3V 1M × 8 / 512K × 16的CMOS闪存EEPROM [3V 1M】8/512K】16 CMOS Flash EEPROM]
分类和应用: 闪存内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 25 页 / 440 K
品牌: ANADIGICS [ ANADIGICS, INC ]
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March 2001
®
AS29LV800
3V 1M × 8/512K × 16 CMOS Flash EEPROM
Features
• Organization: 1M×8/512K×16
• Sector architecture
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
• Hardware RESET pin
- Resets internal state machine to read mode
• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/BY output
• Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
• Low V
CC
write lock-out below 1.5V
• 10 year data retention at 150C
• 100,000 write/erase cycle endurance
Logic block diagram
RY/BY
V
CC
V
SS
RESET
Program/erase
control
Command
register
CE
OE
A-1
Program voltage
generator
Chip enable
Output enable
Logic
STB
Data latch
Sector protect/
erase voltage
switches
Erase voltage
generator
DQ0–DQ15
Pin arrangement
48-pin TSOP
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
44-pin SO
Input/output
buffers
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
BYTE
AS29LV800
V
CC
detector
Timer
Address latch
STB
Y decoder
Y gating
X decoder
Cell matrix
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
V
SS
CE
A0
A0–A18
Selection guide
29LV800-70R
*
Maximum access time
Maximum chip enable access time
Maximum output enable access time
* Regulated voltage range of 3.0 to 3.6V
29LV800-80
80
80
30
29LV800-90
90
90
35
29LV800-120
120
120
50
AS29LV800
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DQ15/A-1
A16
BYTE
V
SS
Unit
ns
ns
ns
t
AA
t
CE
t
OE
70
70
30
3/22/01; V.1.0
Alliance Semiconductor
P. 1 of 25
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