AAT2506
1MHz Step-Down Converter/LDO Regulator
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
Symbol
PGND
LX
VP
VCC
VLDO
OUT
BYP
GND
ENLDO
EN
FB
Function
Step-down converter power ground return pin. Connect to the output and input capaci-
tor return. See section on PCB layout guidelines and evaluation board layout diagram.
Power switching node. Output switching node that connects to the output inductor.
Step-down converter power stage supply voltage. Must be closely decoupled to PGND.
Step-down converter bias supply. Connect to VP.
LDO input voltage; should be decoupled with 1µF or greater capacitor.
300mA LDO output pin. A 2.2µF or greater output low-ESR ceramic capacitor is
required for stability.
Bypass capacitor for the LDO. To improve AC ripple rejection, connect a 10nF capaci-
tor to GND. This will also provide a soft-start function.
LDO ground connection pin.
Enable pin for LDO. When connected low, LDO is disabled and consumes less than
1µA of current.
Step-down converter enable. When connected low, LDO is disabled and consumes
less than 1µA.
Step-down converter feedback input pin. For fixed output voltage versions, this pin is
connected to the converter output, forcing the converter to regulate to the specific volt-
age. For adjustable output versions, an external resistive divider ties to this point and
programs the output voltage to the desired value.
Step-down converter signal ground. For external feedback, return the feedback resis-
tive divider to this ground. For internal fixed version, tie to the point of load return. See
section on PCB layout guidelines and evaluation board layout diagram.
Exposed paddle (bottom). Use properly sized vias for thermal coupling to the ground
plane. See section on PCB layout guidelines.
12
SGND
EP
Pin Configuration
TDFN33-12
(TopView)
PGND
LX
VP
VCC
VLDO
OUT
1
2
3
4
5
6
12
11
10
9
8
7
SGND
FB
EN
ENLDO
GND
BYP
2
2506.2007.05.1.4
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
