AAT3236
300mA CMOS High Performance LDO
tion to ground and the LDO regulator ground con-
nection. When the high load current returns through
this path, a small ripple voltage is created, feeding
into the C
BYP
loop.
Figure 2 shows the preferred method for the
bypass and output capacitor connections. For low
output noise and highest possible power supply
ripple rejection performance, it is critical to connect
the bypass and output capacitor directly to the LDO
regulator ground pin. This method will eliminate
any load noise or ripple current feedback through
the LDO regulator.
Evaluation Board Layout
The AAT3236 evaluation layout (Figures 3, 4, and
5) follows the recommend printed circuit board lay-
out procedures and can be used as an example for
good application layouts.
Note: Board layout shown is not to scale.
V
IN
I
IN
I
LOAD
V
IN
EN
LDO
Regulator
GND
I
GND
V
OUT
BYP
DC INPUT
C
IN
C
BYP
I
BYP
+ noise
C
BYP
GND
LOOP
C
OUT
R
LOAD
I
RIPPLE
GND
R
TRACE
R
TRACE
R
TRACE
R
TRACE
I
LOAD
return + noise and ripple
Figure 1: Common LDO Regulator Layout with C
BYP
Ripple Feedback Loop.
I
IN
I
LOAD
V
IN
EN
GND
V
IN
LDO
Regulator
V
OUT
BYP
DC INPUT
C
IN
I
RIPPLE
I
GND
C
BYP
I
BYP
only
C
OUT
R
LOAD
GND
R
TRACE
R
TRACE
R
TRACE
R
TRACE
I
LOAD
return + noise and ripple
Figure 2: Recommended LDO Regulator Layout.
14
3236.2007.03.1.4
ANALOGICTECH [ ADVANCED ANALOGIC TECHNOLOGIES ]
