Single-cell Li-ion / Li-polymer Battery Protection IC
Rev. E09-06
A7B Series
BLOCK DIAGRAM
Oscillator
V
DD
Counter
Control Circuit
_
+
Over-charge
Detector
Short Detector
+
_
V
M
Level
Shifter
C
O
Charge
Over-current
Detector
+
_
Over-discharge
Detector
Vss
+
_
Discharge
Over-current
Detector
D
O
CHIP PAD CONFIGURATION
No.
1
2
3
4
5
Symbol
D
O
V
M
C
O
V
DD
V
SS
Descriptions
FET gate connection for discharge control (CMOS output)
Voltage monitoring for charger negative
FET gate connection for charge control (CMOS output)
Positive power input
Negative power input
X
173.5
228.5
-1.1
-37.5
-228.5
(Unit :
µm)
Chip pad layout
Y
428.5
-428.5
-428.5
428.5
428.5
V
SS
V
DD
(0,0)
D
O
X
Chip size : 0.7mm×1.1mm
C
O
V
M
Thickness : 0.28mm±0.02mm
Pad size : 0.085mm×0.085mm
Chip base level : V
DD
Y
3
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