APL1581
Application Information (Cont.)
Stability and Output Capacitors (Cont.)
A low-ESR solid tantalum and aluminum electrolytic
capacitor (ESR<1Ω) works extremely well and provides
good transient response and stability over temperature.
Ultra-low-ESR capacitors, such as ceramic chip
capacitors, may promote unstable or under-damped
transient response, but proper ceramic chip capaci-
tors placed near loads can be used as decoupling
capacitors.
The output capacitors are also used to reduce the slew
rate of load current and help the APL1581 to minimize
variations of the output voltage, improving transient
response. For this purpose, the low-ESR capacitors
are recommended.
Input Capacitors
The input capacitors of VCNTL and VIN pins are not
required for stability but for supplying surge currents
during large load transients, and this will prevent the
input rail from drooping and improve the performance
of the APL1581. Because parasitic inductors from volt-
age sources or other bulk capacitors to the VCNTL
and VIN pins will limit the slew rate of the surge cur-
rents during large load transients, resulting in voltage
drop at VIN and VCNTL pins.
A capacitor of 1
µ
F (ceramic chip capacitor) or greater
(aluminum electrolytic capacitor) is recommended and
connected near VCNTL pin. For VIN pin, an aluminum
electrolytic capacitor (>33
µ
F) is recommended. It is
not necessary to use low-ESR capacitors. More ca-
pacitance reduces the variations of the input voltage
at VIN pin.
Layout and Thermal Consideration
The APL1581 series have internal power and thermal
limiting (T
J
=150
o
C typical) circuitry designed to pro-
tect the device under overload conditions. However,
maximum junction temperature ratings should not be
Copyright
©
ANPEC Electronics Corp.
Rev. B.5 - Mar., 2008
10
www.anpec.com.tw
S o l d e ri n g a re a
(1 4 0 m i l x
110mil)
for bottom p a d
1
2
3
4
Vias
Vias
8
7
6
5
exceeded under continuous normal load conditions.
Careful consideration must be given to all sources of
thermal resistance from junction to ambient, includ-
ing junction-to-case, case-to-heat sink interface, and
heat sink resistance itself.
See Figure 3 The SOP-8P is a cost-effective package
featuring a small size as a standard SOP-8 and a
bottom thermal pad to minimize the thermal resistance
of the package, being applicable to high current
applications. The thermal pad is soldered to the top
VOUT plane which may be connected to internal or
bottom VOUT plane by vias to reduce the heat sink
thermal resistance. Therefore, the printed circuit board
(PCB) forms a heat sink and dissipates heat into am-
bient air.
Top layer
VOUT plane
for Heat Dissi p a t i o n
(L a rg e r a re a i s better)
C
OUT
Load
C
CNTL
C
IN
Figure 3 Recommended SOP-8P Layout
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
