APL5330
Ordering and Marking Information
APL5330
Lead Free Code
Handling Code
Temp. Range
Package Code
APL5330KE-TR :
APL5330KAE-TR :
APL5330
XXXXX
Package Code
K : SOP-8
KA : SOP-8-P
Operating Ambient Temp. Range
E : -20 to 70
°
C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device Blank : Original Device
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish;
which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free
products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak
reflow temperature.
Pin Description
PIN NAME
VIN
GND
VCNTL
I/O
I
O
I
DESCRIPTION
Main power input pin. Connect this pin to a voltage source and an input
capacitor. The APL5330 provides current from VIN pin to VOUT pin by
controlling the NPN pass transistor.
Signal ground.
Power input pin for internal control circuitry. Connect this pin to a voltage source
to provide a bias for the internal control circuitry. A bypass capacitor is usually
connected near this pin.
Reference voltage input and active-low shutdown control pin. Connect this pin to
a resistor divider and a capacitor for soft-start and filtering noise purposes.
Pulling and holding the voltage on this pin low by an open-drain transistor shuts
down the output.
Output pin of the regulator. Connect this pin to load. Output capacitors
connected to this pin improves stability and transient response. The output
voltage tracks the reference voltage, and the output pin provides the maximum
current up to 2A.
VREF
I
VOUT
O
Block Diagram
VCNTL
VIN
VREF
Voltage
Regulation
Thermal
Limit
Current
Limit
VOUT
Shutdown
GND
Copyright
©
ANPEC Electronics Corp.
Rev. A.1 - Jun., 2006
2
www.anpec.com.tw
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
