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APL5930 参数 Datasheet PDF下载

APL5930图片预览
型号: APL5930
PDF下载: 下载PDF文件 查看货源
内容描述: 3A ,超低压差( 0.23V典型值)线性稳压器 [3A, Ultra Low Dropout (0.23V Typical) Linear Regulator]
分类和应用: 稳压器
文件页数/大小: 17 页 / 298 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
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APL5930
3A, Ultra Low Dropout (0.23V Typical) Linear Regulator
Features
Compatible with APL5913
Ultra Low Dropout
- 0.23V(typical) at 3A Output Current
Low ESR Output Capacitor (Multi-layer
Chip Capacitors (MLCC)) Applicable
0.8V Reference Voltage
High Output Accuracy
- ±1.5% over Line, Load, and Temperature Range
Fast Transient Response
Adjustable Output Voltage
Power-On-Reset Monitoring on Both VCNTL and
VIN Pins
Internal Soft-Start
Current-Limit and Short Current-Limit Protections
Thermal Shutdown with Hysteresis
Open-Drain VOUT Voltage Indicator (POK)
Low Shutdown Quiescent Current (<30
µA)
Shutdown/Enable Control Function
Simple SOP-8P Package with Exposed Pad
Lead Free and Green Devices Available
(RoHS Compliant)
General Description
The APL5930 is a 3A ultra low dropout linear regulator.
The IC needs two supply voltages, one is a control voltage
(V
CNTL
) for the control circuitry, the other is a main supply
voltage (V
IN
) for power conversion, to reduce power dissi-
pation and provide extremely low dropout voltage.
The APL5930 integrates many functions. A Power-On-
Reset (POR) circuit monitors both supply voltages on
VCNTL and VIN pins to prevent erroneous operations.
The functions of thermal shutdown and current-limit pro-
tect the device against thermal and current over-loads. A
POK indicates the output voltage status with a delay time
set internally. It can control other converter for power
sequence. The APL5930 can be enabled by other power
systems. Pulling and holding the EN voltage below 0.4V
shuts off the output.
The APL5930 is available in a SOP-8P package which
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance to extend power
range of applications.
Applications
Front Side Bus VTT (1.2V/3A)
Note Book PC Applications
Motherboard Applications
Pin Configuration
GND
FB
VOUT
VOUT
1
2
3
4
SOP-8P (Top View)
= Exposed Pad
(connected to VIN plane for better heat dissipation)
8
7
6
5
EN
POK
VCNTL
VIN
Simplified Application Circuit
V
CNTL
V
IN
POK
VCNTL
VIN
POK
VOUT
V
OUT
APL5930
EN
EN
Enable
GND
FB
Optional
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
1
www.anpec.com.tw