APW7068
Block Diagram
VCC12
OCSET
I
OCSET
40uA
REF_OUT
Reference
Buffer
Regulator
Power-On
Reset
BOOT
GND
V
REF
(0.8V)
135%V
REF
X1.35
10V
Soft Start
and
Fault
Logic
O.C.P
Comparator
UGATE
O.V.P
Comparator
PHASE
Sense Low Side
Gate Control
LGATE
Error
Amp 1
PGND
PWM
Comparator
U.V.P
Comparator
10V
:
2
50%V
REF
FBL
V
REF
Oscillator
Sawtooth Wave
(300KHz)
V
REF
Error
Amp 2
DRIVE
FB
COMP
FS_DIS
Absolute Maximum Ratings
Symbol
VCC12
BOOT
UGATE
LGATE
PHASE
DRIVE
VCC12 to GND
BOOT to PHASE
UGATE to PHASE
LGATE to PGND
PHASE to GND
DRIVE to GND
<400ns pulse width
>400ns pulse width
<400ns pulse width
>400ns pulse width
<400ns pulse width
>400ns pulse width
Parameter
Rating
-0.3 to +16
-0.3 to +16
-5 to BOOT+5
-0.3 to BOOT+0.3
-5 to VCC12+5
-0.3 to VCC12+0.3
-5 to +21
-0.3 to 16
12
-0.3 to 7
Unit
V
V
V
V
V
V
V
www.anpec.com.tw
FB, FBL, COMP,
FB, FBL, COMP, FS_DIS to GND
FS_DIS
Copyright
©
ANPEC Electronics Corp.
Rev. A.2 - Jun., 2006
3
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
