APLUS INTEGRATED CIRCUITS INC. APC5800E
ꢀ 3FF6 : PORT_C[7..0] DATA REGISTER. READ AND WRITE.
ꢀ 3FF7 : PORT_C[15..8] DATA REGISTER. READ AND WRITE.
ꢀ 3FF8: PORT_C[7..0] DIRECTION REGISTER. WRITE ONLY.
AN ‘1’ IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT_C TO BE OUTPUT.
THE DEFAULT VALUE FOR EACH BIT IS ZERO.
ꢀ 3FF9: PORT_C[15..8] DIRECTION REGISTER. WRITE ONLY.
AN ‘1’ IN THIS REGISTER WILL SET THE CORRESPONDING PIN OF PORT_C TO BE OUTPUT.
THE DEFAULT VALUE FOR EACH BIT IS ZERO.
ꢀ 3FFA :ADC REGISTER. READ ONLY.
WHEN THE TIMER B NMI OCCURS, THE A/D CONVERSION PROCESS STARTS AND THE S/H
CIRCUIT STOP SAMPLING AND BEGIN HOLDING IT UNTIL THE ADC PROCESS IS FINISHED.
THE ADC INT WILL GENERATE WHEN ADC PROCESS IS FINISHED.
ꢀ 3FFB,3FFC :….NO USE
ꢀ 3FFD : ……NO USE
ꢀ 3FFE: VOICE CHANNEL 1 LOW BYTE AND SYSTEM CONTROL 3. WRITE ONLY.
3FFE
0
1
BIT - 0
SEPARATE MODE FOR DAC
OUTPUT(DEFAULT)
MIX MODE FOR DAC OUTPUT.
BIT - 1
SEPARATE MODE FOR PWM
OUTPUT(DEFAULT)
MIX MODE FOR PWM OUTPUT
BIT - 2
BIT - 3
NO USE(MUST 0)
NO USE (MUST 0)
BIT – 7 ~ 4
VOICE CHANNEL 1 LOW NIBBLE BYTE.
ꢀ 3FFF : VOICE CHANNEL 1 HIGH BYTE. WRITE ONLY.
THE RESOLUTION OF VOICE CHANNEL 1 IS 12 BITS($3FFF,$3FFE BIT7_4). THIS REGISTER
WILL BE TRANSFERRED TO PWM PORT WHILE TIMER_B NMI HAPPEN IN SEPARATE MODE.
9
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APLUS [ APLUS INTERGRATED CIRCUITS ]
