Plerow APL2562
PLL Module
Features
·
+3 dBm Output Level at 2562 MHz
·
Channel Step Size : 1000 kHz
·
2
nd
Description
The plerow PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides
exceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are
available in a surface-mount type package.
TM
Harmonic : < -25 dBc
< 10 ms
·
Spurious Level : < -70 dBc
·
Lock Time :
·
19 mA Current Consumption
Specifications
Parameter
Frequency Range
Output Power
Supply Voltage
Current Consumption
Channel Step Size
2
nd
Harmonics
Spurious Level
Lock Time
Reference Frequency
Reference Input Level
Phase Noise (C / N)
@ 10 kHz
@ 100 kHz
Output Impedance
Operating Temp. Range
Package Type & Size
dBc/Hz
dBc/Hz
Ω
°C
mm
-40
-103
-121
-100
-118
50
25
SMT, 19.0W×19.0L×5.8H
85
-97
-115
Unit
MHz
dBm
V
mA
kHz
dBc
dBc
ms
MHz
dBm
-5
Min.
2537
2
4.7
Typical
2562
3
5.0
19
1000
-35
-78
3
10
0
5
-25
-70
10
Max.
2587
4
5.3
30
More Information
Website: www.asb.co.kr
E-mail: sales@asb.co.kr
Tel: (82) 42-528-7220
Fax: (82) 42-528-7222
ASB, Inc., 4
th
Fl. Venture Town
Bldg, KT HRDC, 367-17
Goijeong-Dong, Seo-Gu,
Daejeon, 302-716, Korea
1) Measurement conditions are as follows: T = 25°C, V
CC
= 5 V, Freq. = 2562 MHz, 50 ohm system.
Outline Drawing
Top View
Bottom View
Pin Configuration
Dimension (mm)
A
B
C
D
E
F
G
H
19.0
19.0
5.8
1.5
0.5
1.75
1.35
15.0
D
A
E
F
I
C
B
Side View
1/1
www.asb.co.kr
H
G
1
2
3
4
9
13
15
16
Others
CLOCK
DATA
ENABLE
OSC IN
VCC (VCO)
RF OUT
VCP (PLL)
LOCK DETECT
Ground
I
0.9
Tolerance:
±
0.2
March 2004
ASB [ ADVANCED SEMICONDUCTOR BUSINESS INC. ]
