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    AX88772A 参数 Datasheet PDF下载

    AX88772A图片预览
    型号： AX88772A
    PDF下载： 下载PDF文件 查看货源
    内容描述： USB 2.0至10 / 100M快速以太网控制器 [USB 2.0 to 10/100M Fast Ethernet Controller]
    分类和应用： 控制器以太网局域网（LAN）标准
    文件页数/大小： 45 页 / 915 K
    品牌： ASIX [ ASIX ELECTRONICS CORPORATION ]
     浏览型号AX88772A的Datasheet PDF文件第2页浏览型号AX88772A的Datasheet PDF文件第3页浏览型号AX88772A的Datasheet PDF文件第4页浏览型号AX88772A的Datasheet PDF文件第5页浏览型号AX88772A的Datasheet PDF文件第7页浏览型号AX88772A的Datasheet PDF文件第8页浏览型号AX88772A的Datasheet PDF文件第9页浏览型号AX88772A的Datasheet PDF文件第10页  
    AX88772A/AX88172A
    Low-pin-count
    USB 2.0 to 10/100M Fast Ethernet Controller
    Table of Contents
    1.0 INTRODUCTION
    ................................................................................................................... 9
    1.1
    1.2
    1.3
    G
    ENERAL
    D
    ESCRIPTION
    ....................................................................................................................................... 9
    B
    LOCK
    D
    IAGRAM
    ................................................................................................................................................ 9
    P
    INOUT
    D
    IAGRAM
    .............................................................................................................................................. 10
    2.0 SIGNAL DESCRIPTION
    ........................................................................................... 14
    2.1
    2.2
    2.3
    AX88772A 64-
    PIN
    P
    INOUT
    D
    ESCRIPTION
    ......................................................................................................... 14
    AX88172A 80-
    PIN
    P
    INOUT
    D
    ESCRIPTION
    ......................................................................................................... 16
    H
    ARDWARE
    S
    ETTING
    F
    OR
    O
    PERATION
    M
    ODE
    A
    ND
    M
    ULTI
    -F
    UNCTION
    P
    INS
    ...................................................... 20
    3.0 FUNCTION DESCRIPTION
    ................................................................................. 20
    3.1
    3.2
    3.3
    3.4
    3.5
    3.6
    3.7
    3.8
    3.9
    3.10
    3.11
    3.12
    3.13
    USB C
    ORE AND
    I
    NTERFACE
    .............................................................................................................................. 20
    10/100M E
    THERNET
    PHY ................................................................................................................................. 20
    MAC C
    ORE
    ....................................................................................................................................................... 20
    O
    PERATION
    M
    ODE
    ............................................................................................................................................. 20
    S
    TATION
    M
    ANAGEMENT
    (STA)......................................................................................................................... 20
    M
    EMORY
    A
    RBITER
    ............................................................................................................................................ 20
    USB
    TO
    E
    THERNET
    B
    RIDGE
    .............................................................................................................................. 20
    S
    ERIAL
    EEPROM L
    OADER
    ............................................................................................................................... 20
    G
    ENERAL
    P
    URPOSE
    I/O...................................................................................................................................... 20
    S
    ERIAL
    I
    NTERFACE
    C
    ONTROLLER
    ...................................................................................................................... 20
    C
    LOCK
    G
    ENERATION
    ......................................................................................................................................... 20
    R
    ESET
    G
    ENERATION
    .......................................................................................................................................... 20
    V
    OLTAGE
    R
    EGULATOR
    ...................................................................................................................................... 20
    4.0 SERIAL EEPROM MEMORY MAP
    ........................................................ 20
    4.1
    D
    ETAILED
    D
    ESCRIPTION
    .................................................................................................................................... 20
    5.0 USB CONFIGURATION STRUCTURE
    .............................................. 20
    5.1
    5.2
    5.3
    USB C
    ONFIGURATION
    ....................................................................................................................................... 20
    USB I
    NTERFACE
    ................................................................................................................................................ 20
    USB E
    NDPOINTS
    ............................................................................................................................................... 20
    6.0 USB COMMANDS
    ............................................................................................................... 20
    6.1
    USB S
    TANDARD
    C
    OMMANDS
    ............................................................................................................................ 20
    6.2
    USB V
    ENDOR
    C
    OMMANDS
    ................................................................................................................................ 20
    6.2.1
    Detailed Register Description .................................................................................................................. 20
    6.2.2
    Command Block Wrapper for Serial Interface ......................................................................................... 20
    6.2.2.1 UART controller
    ................................................................................................................................. 20
    6.2.2.2 I2C controller
    ...................................................................................................................................... 21
    6.2.2.3 SPI controller
    ...................................................................................................................................... 21
    6.3
    I
    NTERRUPT
    E
    NDPOINT
    ....................................................................................................................................... 21
    7.0 EMBEDDED ETHERNET PHY REGISTER
    DESCRIPTION
    ........................................................................................................................................ 21
    7.1
    PHY R
    EGISTER
    D
    ETAILED
    D
    ESCRIPTION
    ........................................................................................................... 21
    7.1.1
    Basic Mode Control Register (BMCR) ..................................................................................................... 21
    7.1.2
    Basic Mode Status Register (BMSR)......................................................................................................... 21
    7.1.3
    PHY Identifier Register 1.......................................................................................................................... 21
    6
    ASIX ELECTRONICS CORPORATION

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