AX88180
High-Performance Non-PCI
32-bit 10/100/1000M Gigabit Ethernet Controller
Document No: AX88180/V1.07
Features
● High-performance non-PCI local bus
16/32-bit SRAM-like host interface (US Patent
Approval)
Support 10/100/1000Mbps data rate with RGMII
or MII in 10/100Mbps data rate.
Support back-pressure flow control for half-duplex
operation
Support big/little endian data bus type
Large embedded SRAM for packet buffers
Support packet length set by software
Support max 4K bytes JUMBO packet
● Support Wake-on-LAN function by following events
Detection of network link-up state
Receipt of a Magic Packet
● Support Magic Packet detection for remote wake-up
after power–on reset
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32K bytes for receive buffer
8K bytes for transmit buffer
Support IP/TCP/UDP checksum offloads
Support interrupt with high or low active trigger
mode
● Highly-integrated Gigabit Ethernet controller
Compatible with IEEE802.3, 802.3u, and 802.3ab ● Support EEPROM interface
standards
Support 10/100/1000Mbps data rate
Support full duplex operation with 1000Mbps data
rate
● Support PCMCIA in 16-bit mode
● Support synchronous or asynchronous mode to host
MCU
● Integrated voltage regulator from 3.3V to 2.5V
Support full and half duplex operations with ● 2.5V for core and 3.3V I/O with 5V tolerance
10/100Mbps date rate
● 128-pin LQFP with CMOS process, RoHS package
Support 10/100/1000Mbps N-way Auto-negotiation
operation
Support IEEE 802.3x flow control for full-duplex
operation
Product Description
The AX88180 is a high-performance and cost-effective non-PCI Gigabit Ethernet controller for various embedded
systems including consumer electronics and home network markets that require a higher bandwidth of network
connectivity. The AX88180 supports 16/32-bit SRAM-like host interface and Gigabit Ethernet MAC, which is
IEEE802.3 10Base-T, IEEE802.3u 100Base-T, and IEEE802.3ab 1000Base-T compatible. The AX88180 supports
full-duplex or half-duplex operation at 10/100Mbps speed and supports full-duplex operation at 1000Mbps speed. The
AX88180 integrates large embedded SRAM for packet buffers to accommodate high bandwidth applications and
supports IP/TCP/UDP checksum to offload processing loading from microprocessor/microcontroller in an embedded
system
System Block Diagram
Always contact ASIX Electronics for possible updates before starting a design.
This data sheet contains new products information. ASIX Electronics reserves the rights to modify product specification
without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the
sale of the product.
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C.
Released Date: 12/30/2008
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
ASIX [ ASIX ELECTRONICS CORPORATION ]
