AX88196
Local CPU BUS MAC Controller
CONTENTS
1.0 INTRODUCTION ...............................................................................................................................................4
1.1 G
ENERAL
D
ESCRIPTION
: .....................................................................................................................................4
1.2 AX88196 B
LOCK
D
IAGRAM
:...............................................................................................................................4
1.3 AX88196 P
IN
C
ONNECTION
D
IAGRAM
................................................................................................................5
1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode.................................................................................6
1.3.2 AX88196 Pin Connection Diagram for 80x86 Mode....................................................................................7
1.3.3 AX88196 Pin Connection Diagram for MC68K Mode.................................................................................8
1.3.4 AX88196 Pin Connection Diagram for MCS-51 Mode ................................................................................9
2.0 SIGNAL DESCRIPTION..................................................................................................................................10
2.1 L
OCAL
CPU B
US
I
NTERFACE
S
IGNALS
G
ROUP
....................................................................................................10
2.2 MII
INTERFACE SIGNALS GROUP
........................................................................................................................11
2.3 EEPROM S
IGNALS
G
ROUP
...............................................................................................................................12
2.4 SNI I
NTERFACE PINS GROUP
..............................................................................................................................12
2.5 S
TANDARD
P
RINTER
P
ORT
I
NTERFACE PINS GROUP
.............................................................................................12
2.6 P
OWER ON CONFIGURATION SETUP SIGNALS PINS GROUP
.....................................................................................13
2.7 M
ISCELLANEOUS PINS GROUP
............................................................................................................................13
3.0 MEMORY AND I/O MAPPING ......................................................................................................................15
3.1 EEPROM M
EMORY
M
APPING
..........................................................................................................................15
3.2 I/O M
APPING
....................................................................................................................................................15
3.3 SRAM M
EMORY
M
APPING
...............................................................................................................................15
4.0 REGISTERS OPERATION..............................................................................................................................16
4.1 C
OMMAND
R
EGISTER
(CR) O
FFSET
00H (R
EAD
/W
RITE
) ...................................................................................18
4.2 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) O
FFSET
07H (R
EAD
/W
RITE
)......................................................................18
4.3 I
NTERRUPT MASK REGISTER
(IMR) O
FFSET
0FH (W
RITE
)..................................................................................19
4.4 D
ATA
C
ONFIGURATION
R
EGISTER
(DCR) O
FFSET
0EH (W
RITE
)........................................................................19
4.5 T
RANSMIT
C
ONFIGURATION
R
EGISTER
(TCR) O
FFSET
0DH (W
RITE
).................................................................19
4.6 T
RANSMIT
S
TATUS
R
EGISTER
(TSR) O
FFSET
04H (R
EAD
) .................................................................................20
4.7 R
ECEIVE
C
ONFIGURATION
(RCR) O
FFSET
0CH (W
RITE
) ...................................................................................20
4.8 R
ECEIVE
S
TATUS
R
EGISTER
(RSR) O
FFSET
0CH (R
EAD
) ...................................................................................20
4.9 I
NTER
-
FRAME GAP
(IFG) O
FFSET
16H (R
EAD
/W
RITE
) .......................................................................................21
4.10 I
NTER
-
FRAME GAP
S
EGMENT
1(IFGS1) O
FFSET
12H (R
EAD
/W
RITE
)................................................................21
4.11 I
NTER
-
FRAME GAP
S
EGMENT
2(IFGS2) O
FFSET
13H (R
EAD
/W
RITE
)................................................................21
4.12 MII/EEPROM M
ANAGEMENT
R
EGISTER
(MEMR) O
FFSET
14H (R
EAD
/W
RITE
)...............................................21
4.13 T
EST
R
EGISTER
(TR) O
FFSET
15H (W
RITE
) ....................................................................................................21
4.14 SPP D
ATA
P
ORT
R
EGISTER
(SPP_DPR) O
FFSET
18H (R
EAD
/W
RITE
)...............................................................22
4.15 SPP S
TATUS
P
ORT
R
EGISTER
(SPP_SPR) O
FFSET
19H (R
EAD
)........................................................................22
4.16 SPP C
OMMAND
P
ORT
R
EGISTER
(SPP_CPR) O
FFSET
1AH (R
EAD
/W
RITE
) ......................................................22
5.0 CPU I/O READ AND WRITE FUNCTIONS ..................................................................................................23
5.1 ISA
BUS TYPE ACCESS FUNCTIONS
. ....................................................................................................................23
5.2 80186 CPU
BUS TYPE ACCESS FUNCTIONS
. ........................................................................................................23
5.3 MC68K CPU
BUS TYPE ACCESS FUNCTIONS
.......................................................................................................24
5.4 MCS-51 CPU
BUS TYPE ACCESS FUNCTIONS
. .....................................................................................................24
6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................25
6.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
.........................................................................................................................25
6.2 G
ENERAL
O
PERATION
C
ONDITIONS
...................................................................................................................25
6.3 DC C
HARACTERISTICS
......................................................................................................................................25
6.4 A.C. T
IMING
C
HARACTERISTICS
........................................................................................................................26
6.4.1 XTAL / CLOCK.........................................................................................................................................26
2
ASIX ELECTRONICS CORPORATION
ASIX [ ASIX ELECTRONICS CORPORATION ]
