CONFIDENTIAL
AX88141
BR_A<15>
BR_A<14>
BR_A<13>
BR_A<12>
BR_A<11>
BR_A<10>
BR_A<9>
BR_A<8>
BR_A<7>
BR_A<6>
BR_A<5>
BR_A<4>
BR_A<3>
BR_A<2>
BR_A<1>
BR_A<0>
BR_D<7>
BR_D<6>
BR_D<5>
BR_D<4>
BR_D<3>
BR_D<2>
BR_D<1>
BR_D<0>/
SR_DO
BR_CE#
SR_CK
SR_CS
SR_DI
GENP<1>
GENP<0>
O
104,
103,
102,
101,
100,
99,
98,
97,
96,
95,
94,
93,
92,
91,
90,
89
88,
86,
85,
84,
83,
82,
81,
73
78
76
77
79
106,
105
Boot ROM address lines bit 15 to bit 0.
PRELIMINARY
I
Boot ROM data lines bit 7 to bit 0.
O
O
O
O
I/O
Serial ROM data-out signal.
Boot ROM chip enable.
Serial ROM clock signal.
Serial ROM chip-select signal.
Serial ROM data-in signal.
General-purpose pins can be used by software as either status pins or control pins. These pins can be
configured by software to perform either input or output functions.
Tab - 2 Boot ROM , Serial ROM , General-purpose signals group
2.4 MII interface signals group
SIGNAL
TYPE PIN
NUMBER
FOR 160 PIN
I
I
I
113
114
111
DESCRIPTION
COL
CRS
RXDV
RXER
I
109
MDC
MDIO
RXCLK
RXD<3>
RXD<2>
RXD<1>
RXD<0>
TXCLK
TXD<3>
TXD<2>
TXD<1>
TXD<0>
TXEN
O
I/O
I
I
108
107
115
119,
118,
117,
116
121
128,
127,
125,
124
123
Collision detected is asserted when detected by an external physical layer protocol(PHY)
device.
Carrier sense is asserted by the PHY when the media is active.
Data valid is asserted by an external PHY when receive data is present on the RXD lines
and is deasserted at the end of the packet. This signal should be synchronized with the
RXCLK signal.
Receive error asserts when a data decoding error is detected by an external PHY device.
This signal is synchronized to RXCLK and can be asserted for a minimum of one receive
clock. When asserted during a packet reception, it sets the cyclic redundancy check(CRC)
error bit in the receive descriptor (RDESO).
MII management data clock is sourced by the AX88141 to the PHY devices as a timing
reference for the transfer of information on the MII_MDIO signal.
MII management data input/output transfers control information and status between the
PHY and the AX88141.
Supports either the 25-MHZ or 2.5-MHZ receive clock. This clock is recovered by the
PHY.
Four parallel receive data lines When MII mode is selected. This data is driven by an
external PHY that attached the media and should be synchronized with the RXCLK signal.
I
O
Supports the 25-MHZ or 2.5-MHZ transmit clock supplied by the external physical layer
medium dependent (PMD) device. This clock should always be active.
Four parallel transmit data lines. This data is synchronized to the assertion of the TXCLK
signal and is latched by the external PHY on the rising edge of the TXCLK signal.
O
Transmit enable signals that the transmit is active to an external PHY device.
Tab - 3 MII interface signals group
12
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