Features
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Low-voltage and Standard-voltage Operation
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– 1.8 (V
CC
= 1.8V to 3.6V)
Internally Organized as 32,768 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (3.6V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 40 Years
Extended Temperature and Lead-free/Halogen-free Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP, and 8-ball
dBGA2
TM
Packages
Two-wire Serial
EEPROM
256K (32,768 x 8)
Description
The AT24C256B provides 262,144 bits of serial electrically erasable and programma-
ble read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The
device’s cascadable feature allows up to eight devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (1.8V
to 3.6V) version.
Table 1.
Pin Configurations
Pin Name
Function
A0
A1
A2
GND
AT24C256B
Preliminary
8-lead
PDIP
8-lead SOIC
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0–A2
SDA
SCL
WP
NC
GND
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
Ground
8-lead
dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A0
A1
A2
GND
A1
A2
GND
8-lead
TSSOP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Bottom View
8-lead
MAP
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
Bottom View
Rev. 5080A–SEEPR–9/04
1
ATMEL [ ATMEL CORPORATION ]
