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AT25040AN-10SU-2.7 参数 Datasheet PDF下载

AT25040AN-10SU-2.7图片预览
型号: AT25040AN-10SU-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: SPI串行EEPROM [SPI Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 22 页 / 571 K
品牌: ATMEL [ ATMEL CORPORATION ]
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Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 2.7 (V
CC
= 2.7V to 5.5V)
– 1.8 (V
CC
= 1.8V to 5.5V)
20 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3) and 8-
lead TSSOP Packages
Die Sales: Wafer Form, Waffle Pack, Bumped Wafers
SPI Serial
EEPROM
1K (128x8)
2K (256x8)
4K (512x8)
Description
The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically eras-
able programmable read-only memory (EEPROM) organized as 128/256/512 words of
8 bits each. The device is optimized for use in many industrial and commercial appli-
c a t i o n s w h e r e l ow - p ow e r a n d l ow - vo l t a g e o p e ra t i o n a r e e s s e n t i a l . T h e
AT25010A/020A/040A is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC,
8-lead Ultra Thin
mini-MAP (MLP 2x3)
, and 8-lead TSSOP packages.
The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate Program Enable and Program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 1.
Pin Configuration
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
8-lead
Ultra Thin mini-MAP (MLP 2x3)
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
C S
SO
W P
G N D
8-lead
TSSOP
1
2
3
4
8
7
6
5
V
H
S
S
C C
O L
C K
I
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead
PDIP
C S
SO
W P
G N D
8-lead SOIC
1
2
3
4
8
7
6
5
V
H
S
S
C C
O L
C K
I
AT25010A
AT25020A
AT25040A
Bottom view
3348J–SEEPR–8/06