Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR.
POF is set to “1” during power up. It can be set and rest under software control and is not
affected by reset.
Table 3. AUXR1: Auxiliary Register 1
AUXR1
Address = A2H
Reset Value = XXXXXXX0B
Not Bit Addressable
–
–
–
5
–
4
–
3
–
2
–
1
DPS
0
Bit
7
6
–
Reserved for future expansion
Data Pointer Register Select
DPS
DPS
0
1
Selects DPTR Registers DP0L, DP0H
Selects DPTR Registers DP1L, DP1H
Memory
Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through
FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are
directed to external memory.
Data Memory
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct
and indirect addressing modes. Stack operations are examples of indirect addressing, so the
128 bytes of data RAM are available as stack space.
Watchdog
Timer
(One-time
Enabled with
Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a
user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, it will increment every machine cycle while the oscillator is running.
The WDT timeout period is dependent on the external clock frequency. There is no way to dis-
able the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment
every machine cycle while the oscillator is running. This means the user must reset the WDT
at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.
When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET
pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it
should be serviced in those sections of code that will periodically be executed within the time
required to prevent a WDT reset.
8
AT89S51
2487B–MICRO–12/03
ATMEL [ ATMEL ]
