Instruction Set for the AT93C56A and AT93C66A
Instruction
READ
EWEN
ERASE
WRITE
ERAL
SB
1
1
1
1
1
Op
Code
10
00
11
01
00
Address
x8
A
8
– A
0
11XXXXXXX
A
8
– A
0
A
8
– A
0
10XXXXXXX
x 16
A
7
– A
0
11XXXXXX
A
7
– A
0
A
7
– A
0
10XXXXXX
D
7
– D
0
D
15
– D
0
x8
Data
x 16
Comments
Reads data stored in memory, at
specified address.
Write enable must precede all
programming modes.
Erases memory location A
n
– A
0
.
Writes memory location A
n
– A
0
.
Erases all memory locations. Valid
only at V
CC
= 4.5V to 5.5V.
D
7
– D
0
D
15
– D
0
Writes all memory locations. Valid
only at V
CC
= 5.0V ±10% and Disable
Register cleared.
Disables all programming instructions.
WRAL
EWDS
Note:
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
The X’s in the address field represent don’t care values and must be clocked.
Functional Description
The AT93C56A/66A is accessed via a simple and versatile 3-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor.
A valid instruction starts with a rising edge of CS
and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ):
The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the inter-
nal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between mem-
ory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN):
To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or V
CC
power is removed from the part.
ERASE (ERASE):
The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
).
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
5
3378F–SEEPR–04/04
ATMEL [ ATMEL CORPORATION ]
