AS5C512K8EC-30LE/XT 参数 Datasheet PDF下载

SRAM

Austin Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

VCC

GND

AS5C512K8

DQ8

INPUT BUFFER

ROW DECODER

I/O

CONTROLS

4,194,304-BIT

MEMORY ARRAY

1024 ROWS X

4096 COLUMNS

A0-A18

DQ1

CE\

COLUMN DECODER

OE\

WE\

*POWER

DOWN

*On the low voltage Data Retention option.

PIN FUNCTIONS

A0 - A18

Address Inputs

Write Enable

Chip Enable

Output Enable

Data Inputs/Outputs

Power

Ground

No Connection

TRUTH TABLE

MODE

OE\ CE\ WE\

STANDBY

X

H

X

READ

L

L

H

NOT SELECTED H

L

H

WRITE

X

L

L

X = Don’t Care

WE\

I/O

HIGH-Z

Q

HIGH-Z

D

POWER

STANDBY

ACTIVE

ACTIVE

ACTIVE

CE\

OE\

I/O

0

- I/O

7

V

CC

V

SS

NC

AS5C512K8

Rev. 7.0 05/08

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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