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AS5C512K8F-12E/IT 参数 Datasheet PDF下载

AS5C512K8F-12E/IT图片预览
型号: AS5C512K8F-12E/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×8 SRAM高速SRAM和革命引脚 [512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT]
分类和应用: 静态存储器
文件页数/大小: 17 页 / 229 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................................... Vss to 3.0V
Input rise and fall times ......................................................... 3ns
Input timing reference levels ............................................... 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1 and 2
AS5C512K8
Q
167 ohms
1.73V
C=30pF
Q
167 ohms
1.73V
C=5pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
4.
5.
6.
All voltages referenced to V
SS
(GND).
-2V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
WE\ is HIGH for READ cycle.
9.
10.
11.
12.
13.
14.
15.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
Chip enable and write enable can initiate and
terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
Output enable (OE\) is active (LOW).
ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
7.
8.
DATA RETENTION ELECTRICAL CHARACTERISTICS
(L Version Only)
DESCRIPTION
Vcc for Retention Data
Data Retention Current
Chip Deselect to Data
Operation Recovery Time
CONDITIONS
CE\ > V
CC
-0.2V
V
IN
> V
CC
-0.2 or 0.2V
Vcc = 2.0V
SYM
V
DR
I
CCDR
t
CDR
t
R
0
10
MIN
2
800
MAX
UNITS
V
uA
ns
ms
4
4, 11
NOTES
AS5C512K8
Rev. 7.0 05/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5