FLASH
Austin Semiconductor, Inc.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete. Toggle
Bit I may be read at any address, and is valid after the rising
edge of the final WEx\ pulse in the command sequence (prior to
the program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause I/O6 to
toggle. (The system may use either OE\ or CEx\ to control the
read cycles.) When the operation is complete, I/O6 stops
toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles or approximately
100 ms, then returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases
the unprotected sectors, and ignores the selected sectors that
are protected.
If a program address falls within a protected sector, I/O6
toggles for approximately 2 ms after the program command
sequence is written, then returns to reading array data.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram.
AS8F128K32
I/O5 through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
FIGURE 4: Toggle Bit Algorithm
Reading Toggle Bit I/O6
Refer to Figure 4 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O7–I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7–I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again whether
the toggle bit is toggling, since the toggle bit may have stopped
toggling just as I/O5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the program
or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O5 has not gone
high. The system may continue to monitor the toggle bit and
*NOTE:
applies to every 8th byte.
AS8F128K32
Rev. 2.7 09/07
*
NOTES:
1. Read toggle bit twice to determine whether or not it is toggling. See
text.
2. Recheck toggle bit because it may stop toggling as I/O5 changes to “1”.
See text.
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