AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
1M x 32 FLASH
FLASH MEMORY MODULE
AVAILABLE AS MILITARY
SPECIFICATIONS
• Military Processing (MIL-PRF-38534, para 1.2)
•
Temperature Range -55
o
C to 125
o
C
AS8F1M32
FLASH
FIGURE 1: PIN ASSIGNMENT
(Top View)
68 Lead CQFP
RESET\
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
VCC
08
07
06
05
02
01
67
65
09
04
03
68
66
64
63
62
I/O0
I/O1
I/02
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/012
I/O13
I/O14
I/O15
61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
78
57
76
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
FEATURES
• Fast access times of 90ns, 120ns, and 150ns
• 5.0V ±10%, single power supply operation
• Low power consumption typical: 4µA typical CMOS stand-by
* ICC(active) <120mA for READ/WRITE
• 20 year DATA RETENTION at 125
o
C
• 1,000,000 program/erase cycles
• 16 equal sectors of 64 Kbytes each
• Any combination of sectors can be erased
• Group sector protection
• Supports FULL chip erase
• Compatible with JEDEC standards
• Embedded erase and program algorithms
• Data\ polling and toggle bits for detection of program or erase
cycle completion.
• Erase suspend/resume
• Hardware reset pin (RESET\)
• Built in decoupling caps and multiple ground pins for low
noise operation
• Separate power and ground planes to improve noise immunity
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VCC
A11
A12
A13
A14
A15
A16
CS1\
OE\
CS2\
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8F1M32 is a 32 Mbit, 5.0 volt-
only Flash memory. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply. The AS8F1M32
offers an access time of 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention, the device has
separate chip enable (CE\), write enable (WE\) and output enable (OE\)
controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC
single-power-supply FLASH standard. Commands are written to the
command register using standard microprocessor write timings.
Register contents serve as input to an internal state-matching that
controls the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading
from other FLASH or EPROM devices.
Device programming occurs by executing the program command
sequence. This initiates the Embedded Program algorithm - an internal
algorithm that automatically time the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm - an internal algorithm that
automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies proper cell
margin.
The host system can detect whether a program or erase operation is
complete by observing the DQ7 (DATA\ Polling) and DQ6 (toggle)
status bits. After a program or erase cycle has been completed, the
device is ready to read array data or accept another command.
(continued on page 2)
OPTION
• Timing
90ns
120ns
150ns
• Packages
Ceramic Quad Flat Pack (0.88" sq)
- MAX height .140"
- Stand-off Height .035" min
MARKING
-90
-120
-150
QT
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS8F1M32
Rev. 1.5 09/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
A17
WE2\
WE3\
WE4\
A18
A19
NC
43
AUSTIN [ AUSTIN SEMICONDUCTOR ]
