AUSTIN SEMICONDUCTOR, INC.
FLASH
AS8FLC1M32
Austin Semiconductor, Inc.
When the Embedded Program algorithm is complete, the device
then returns to READING array data and addresses are no
longer latched. The system can determine the status of the
program operation by using DQ31, DQ30, DQ23, DQ22, DQ15.
DQ14, DQ7, DQ6, or RY/BY\.
Reset Command
WRITING the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The RESET command may be WRITTEN between the sequence
cycles in an ERASE command sequence before ERASING
begins. This resets the device to READING array data. Once
ERASURE begins, the device ignores RESET command
requests until the first initiation of the operation has completed.
Any commands WRITTEN to the device during the Embedded
Program algorithm are ignored. Note that a HARDWARE
RESET immediately terminates the programming operation. The
Byte Program command sequence should be reinitiated once
the device has reset to READING Array data, to ensure data
integrity.
The RESET command may be WRITTEN between the sequence
cycles in a program command sequence and before
programming begins. This RESETS the device to READING
Array data. Once programming begins, the device ignores
additional RESET command requests until the current operation
has completed.
PROGRAMMING is allowed in any sequence and across
Sector Boundaries. A bit cannot be PROGRAMMED from a
“0” back to a “1”, this can only be accomplished via an ERASE
operation.
Unlock Bypass Command Sequence
The RESET command may be written between the sequence
cycles in an Autoselect command sequence. Once in the
Autoselect Mode, the reset command must be WRITTEN to
return to READINGArray data.
The UNLOCK BYPASS feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The UNLOCK BYPASS command
sequence is initiated by first WRITING two UNLOCK cycles.
This is followed by a third WRITE cycle containing the
UNLOCK BYPASS command, 20h. The device then enters the
UNLOCK BYPASS mode. A two-cycle UNLOCK BYPASS
command operation is all that is required to PROGRAM in this
mode. The first cycle in this sequence contains the UNLOCK
BYPASS program command, A0h; the second cycle contains
the program address and data. Additional data is
PROGRAMMED in the same manner. This mode dispenses
with the initial two UNLOCK cycles required in the standard
PROGRAM command sequence. The first cycle must contain
the data 90h; the second cycle the data 00h. Addresses are
don’t care fore both cycles. The device then returns to
READINGArray data.
Autoselect Command Sequence
The Autoselect command sequence allows the host system to
access the manufacturer and device codes, allowing the user
determination as to whether or not a Sector is protected. This
method is an alternative to DEVICE PROGRAMMERS but
requires VID on Address bit 9 (A9).
The Autoselect command sequence is initiated by WRITING
two UNLOCK cycles, followed by the AUTOSELECT
COMMAMD. The device then enters the AUTOSELECT
mode, and the system may read at any address, any number of
times, without initiating another command.
A READ cycle at Address XX00h retrieves the manufacturer
code. A READ cycle at Address XX01h returns the device
code. A READ cycle containing a Sector Address (SA) and
the address 02h returns 01h if that sector is protected, or 00h if
it is un-protected.
Chip Erase Command Sequence
CHIP ERASE is a six-bus cycle operation. The CHIP ERASE
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional UNLOCK
WRITE cycles are then followed by the chip ERASE command,
which in turn invokes the Embedded ERASE algorithm. The
device does not require the system to PRE-PROGRAM prior to
ERASE. The Embedded ERASE algorithm automatically PRE-
PROGRAMS and VERIFIES the entire Array for an all Zero
data pattern prior to electrical ERASE. The system is not
required to provide any controls or timing during these
operations.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock WRITE
cycles, followed by the PROGRAM set-up command. The
program address and data are WRITTEN next, which in turn
initiates the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated PROGRAM pulses
and verifies the programmed cell margin.
Any commands WRITTEN to the chip during the Embedded
ERASE operation are ignored. Note that a HARDWARE RESET
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8FLC1M32B
Rev. 3.3 05/08
8
AUSTIN [ AUSTIN SEMICONDUCTOR ]
