SRAM
Austin Semiconductor, Inc.
CAPACITANCE TABLE
(V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C)
SYMBOL
C
ADD
C
OE
C
WE,
C
CE
C
IO
PARAMETER
A0 - A18 Capacitance
OE\ Capacitance
WE\ and CE\ Capacitance
I/O 0- I/O 31 Capacitance
MAX
40
40
20
20
UNITS
pF
pF
pF
pF
NOTES
4
4
4
4
AS8S128K32
TRUTH TABLE
MODE
Read
Write
Standby
Not Selected
OE\
L
X
X
H
CE\
L
L
H
L
WE\
H
L
X
H
I/O
Q
D
HIGH Z
HIGH Z
POWER
ACTIVE
ACTIVE
STANDBY
ACTIVE
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels........................................VSS to 3V
Input rise and fall times..........................................5ns
Input timing reference levels.................................1.5V
Output reference levels........................................1.5V
Output load.............................................See Figures 1
Vz = 1.5V
(Bipolar
Supply)
I
OL
Current Source
Device
Under
Test
-
+
+
Ceff = 50pf
Current Source
I
OH
NOTES:
Vz is programable from -2V to + 7V.
I
OL
and I
OH
programmable from 0 to 16 mA.
Vz is typically the midpoint of V
OH
and V
OL
.
I
OL
and I
OH
are adjusted to simulate a typical resistive load
circuit.
Figure 1
AS8S128K32
Rev. 4.0 5/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
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