Austin Semiconductor, Inc.
WRITE CYCLE NO. 1
12
(Chip Enabled Controlled)
WC
tWC
MT5C1001
Limited Availability
SRAM
t
ADDRESS
t
AW
tAW
t
AS
tAS
CE\
WE\
t
CW
tCW
t
WP
tWP1
t
DS
tDS
AH
tAH
t
D
Q
DATA VAILD
HIGH Z
WRITE CYCLE NO. 2
7, 12
(Write Enabled Controlled)
t
WC
tWC
ADDRESS
t
AW
tAW
t
CW
tCW
t
AH
tAH
CE\
t
AS
tAS
t
WP
tWP1
t
DS
t
DH
tDH
WE\
Q
HIGH-Z
DON’T CARE
UNDEFINED
NOTE:
Output enable (OE\) is inactive (HIGH).
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
65432111
1
422
3
65432111
1
422
3
65432111
1
422
3
65432111
1
422
3
4321
1
4321
4321
432
321
321
321
6
431113210987654321
254
436113210987654321
1 54
2
436113210987654321
1 54
2
431113210987654321
254
6
D
t
HZWE
DATA VALID
2
32109876543210987654321
1
1
1
321098765432109876543211
1
32109876543210987654321
098765432121098765432109876543210987654321
1
1
1
1
098765432121098765432109876543210987654321
1
t
DH
tDH
t
LZWE
109876543210987654321
1
1
1
109876543210987654321
1
1
987654321
987654321
987654321
11
17
21
21
1
276543210987654321
216543210987654321
276543210987654321