Austin Semiconductor, Inc.
MT5C1001
Limited Availability
SRAM
FUNCTIONAL BLOCK DIAGRAM
V
CC
Vss
A
6
A
5
ROW DECODER
1,048,576-BIT
MEMORY ARRAY
512 rows x 2048
columns
D
A
3
A
15
A
14
A
13
A
8
A
7
I/O CONTROL
A
4
Q
CE\
WE\
POWER
DOWN
COLUMN DECODER
A
2
A
1
A
16
A
0
A
17
A
18
A
19
A
10
A
9
A
12
A
11
TRUTH TABLE
MODE
STANDBY
READ
WRITE
CE\
H
L
L
WE\
X
H
L
OUTPUT
HIGH-Z
Q
HIGH-Z
POWER
STANDBY
ACTIVE
ACTIVE
PIN ASSIGNMENTS
PIN
A
0
-A
19
WE\
CE\
D
Q
NC
V
CC
V
SS
ASSIGNMENT
Address Inputs
Write Enable
Chip Enable
Data Input
Data Output
No Connection
+5V Power Supply
Ground
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
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