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MT5C1001DCJ-20/XT 参数 Datasheet PDF下载

MT5C1001DCJ-20/XT图片预览
型号: MT5C1001DCJ-20/XT
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×1 SRAM SRAM存储器阵列 [1M x 1 SRAM SRAM MEMORY ARRAY]
分类和应用: 存储静态存储器
文件页数/大小: 13 页 / 95 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
MT5C1001
Limited Availability
SRAM
167Ω
Q
30pF
V
TH
= 1.73V Q
167Ω
5pF
V
TH
= 1.73V
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-3V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE
, t
LZWE
, t
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
4.
5.
6.
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
and
t
HZOE
is less than t
LZOE
.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC
= Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
CONDITIONS
CE\ > (V
CC
- 0.2V)
and
V
IN
> (V
CC
- 0.2V)
or < 0.2V
SYMBOL
V
DR
I
CCDR
V
CC
= 2V
V
CC
= 3V
t
MIN
2
MAX
--
1.0
1.5
UNITS
V
mA
mA
ns
NOTES
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CDR
t
0
--
t
4
4, 11
R
RC
ns
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
V
DR
> 2V
4.5V
t
R
V
DR
MT5C1001
Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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V
IH
V
IL
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