SRAM
Austin Semiconductor, Inc.
256K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883
MT5C1005
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE\
OE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE\
OE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
FEATURES
High Speed: 20, 25, 35, and 45
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE\
OE\
Vss
•
•
•
•
32-Pin Flat Pack (F)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
32-Pin LCC (ECW)
A9
A8
A7
NC
Vcc
A6
A5
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-20
-25
-35
-45
-55*
-70*
4 3 2 1 31 32 30
A10
A11
A12
A13
A14
A15
A16
A17
CE\
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A2
A4
A3
A1
A0
NC
NC
NC
DQ4
14 15 16 17 18 19 20
DQ3
DQ2
DQ1
WE\
Vss
OE\
NC
• Package(s)
Ceramic DIP (400 mil)
C
Ceramic Quad LCC
(contact factory)
ECW
Ceramic LCC
EC
Ceramic Flatpack
F
Ceramic SOJ
DCJ
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
No. 109
No. 206
No. 207
No. 303
No. 501
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE\) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1005
Rev. 3.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
AUSTIN [ AUSTIN SEMICONDUCTOR ]
