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5962-8876802KPC 参数 Datasheet PDF下载

5962-8876802KPC图片预览
型号: 5962-8876802KPC
PDF下载: 下载PDF文件 查看货源
内容描述: 密封式低中频,宽VCC逻辑门光电耦合器 [Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers]
分类和应用: 光电输出元件
文件页数/大小: 14 页 / 365 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
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HCPL-520x, HCPL-523x, HCPL-623x, HCPL-625x,
5962-88768 and 5962-88769
Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers
Data Sheet
Description
�½he�½e unit�½ are �½ingle�½�½ dual and quad channel�½�½ hermeti�½
call�½�½ �½ealed o�½tocou�½ler�½. �½he �½roduct�½ are ca�½able o�½
o�½eration and �½torage over the �½ull militar�½�½ tem�½erature
range and can be �½urcha�½ed a�½ either �½tandard �½roduct
or with �½ull M�½�½�½P�½�½�½�½�½�½�½�½�½ Cla�½�½ �½evel �½�½ or �½ te�½ting
or �½rom the a�½�½ro�½riate DSCC Drawing. �½ll device�½ are
manu�½actured and te�½ted on a M�½�½�½P�½�½�½�½�½�½�½�½�½ certified
line and are included in the DSCC �½ualified Manu�½actur�½
er�½ �½i�½t �½M�½�½�½�½�½�½�½�½ �½or �½�½�½�½brid Microcircuit�½.
Each channel contain�½ an �½l�½a�½�½ light emitting diode
which i�½ o�½ticall�½�½ cou�½led to an integrated high gain
�½hoton detector. �½he detector ha�½ a thre�½hold with h�½�½�½�½
tere�½i�½ which �½rovide�½ differential mode noi�½e immunit�½�½
and eliminate�½ the �½otential �½or out�½ut �½ignal chatter.
�½he detector in the �½ingle channel unit�½ ha�½ a tri�½�½tate
out�½ut �½tage which allow�½ �½or direct connection to data
bu�½e�½. �½he out�½ut i�½ noninverting. �½he detector �½C ha�½
an internal �½hield that �½rovide�½ a guaranteed common
mode tran�½ient immunit�½�½ o�½ u�½ to �½0�½�½000 �½�½�½�½. �½m�½roved
�½ower �½u�½�½l�½�½ rejection eliminate�½ the need �½or �½�½ecial
�½ower �½u�½�½l�½�½ b�½�½�½a�½�½ �½recaution�½.
Features
Dual Marked with Device Part Number and DSCC
Standard Microcircuit Drawing
Manu�½actured and �½e�½ted on a M�½�½�½P�½�½�½�½�½�½�½�½�½ Certi�½
Manu�½actured and �½e�½ted on a M�½�½�½P�½�½�½�½�½�½�½�½�½ Certi�½
fied �½ine
�½M�½�½�½�½�½�½�½�½�½�½ Cla�½�½ �½�½ and �½
�½M�½�½�½�½�½�½�½�½�½�½ Cla�½�½ �½�½ and �½
�½our �½�½ermeticall�½�½ Sealed Package Configuration�½
�½our �½�½ermeticall�½�½ Sealed Package Configuration�½
Per�½ormance �½uaranteed over �½�½�½�½C to �½�½�½�½�½C
Per�½ormance �½uaranteed over �½�½�½�½C to �½�½�½�½�½C
�½ide �½
CC
�½ange (�½�½.�½ to �½0 �½)
�½ide �½
�½�½0 n�½ Ma�½imum Pro�½agation Dela�½�½
�½�½0 n�½ Ma�½imum Pro�½agation Dela�½�½
CM�½�½�½ �½�½ �½0�½�½000 �½�½�½�½ �½�½�½�½ical
CM�½�½�½ �½�½ �½0�½�½000 �½�½�½�½ �½�½�½�½ical
�½�½00 �½dc �½ith�½tand �½e�½t �½oltage
�½�½00 �½dc �½ith�½tand �½e�½t �½oltage
�½hree State �½ut�½ut �½vailable
�½hree State �½ut�½ut �½vailable
�½�½igh �½adiation �½mmunit�½�½
�½�½igh �½adiation �½mmunit�½�½
�½�½CP�½�½�½�½00�½�½�½ �½unction Com�½atibilit�½�½
�½�½CP�½�½�½�½00�½�½�½ �½unction Com�½atibilit�½�½
�½eliabilit�½�½ Data �½vailable
�½eliabilit�½�½ Data �½vailable
Com�½atible with �½S�½�½�½�½�½ �½�½�½�½�½ and CM�½S �½ogic
Com�½atible with �½S��½�½�½�½�½ �½�½�½�½�½ and CM�½S �½ogic
Applications
Militar�½�½ and S�½ace
�½�½igh �½eliabilit�½�½ S�½�½�½tem�½
�½ran�½�½ortation and �½i�½e Critical S�½�½�½tem�½
�½�½igh S�½eed �½ine �½eceiver
�½�½olated Bu�½ Driver (Single Channel)
Pul�½e �½ran�½�½ormer �½e�½lacement
�½round �½oo�½ Elimination
�½�½ar�½h �½ndu�½trial Environment�½
Com�½uter�½Peri�½heral �½nter�½ace�½
Note�½�½ �½ 0.�½ m�½ b�½�½�½a�½�½ ca�½acitor mu�½t be connected between �½
CC
and �½ND �½in�½.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.